{"id":"https://openalex.org/W2153643257","doi":"https://doi.org/10.1109/iccad.2003.1257805","title":"A framework for designing reusable analog circuits","display_name":"A framework for designing reusable analog circuits","publication_year":2004,"publication_date":"2004-05-13","ids":{"openalex":"https://openalex.org/W2153643257","doi":"https://doi.org/10.1109/iccad.2003.1257805","mag":"2153643257"},"language":"en","primary_location":{"id":"doi:10.1109/iccad.2003.1257805","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad.2003.1257805","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5009759139","display_name":"D. Liu","orcid":null},"institutions":[{"id":"https://openalex.org/I97018004","display_name":"Stanford University","ror":"https://ror.org/00f54p054","country_code":"US","type":"education","lineage":["https://openalex.org/I97018004"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"D. Liu","raw_affiliation_strings":["Computer Systems Laboratory, University of Stanford, Stanford, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Systems Laboratory, University of Stanford, Stanford, CA, USA","institution_ids":["https://openalex.org/I97018004"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5006919236","display_name":"S. Sidiropoulos","orcid":null},"institutions":[{"id":"https://openalex.org/I97018004","display_name":"Stanford University","ror":"https://ror.org/00f54p054","country_code":"US","type":"education","lineage":["https://openalex.org/I97018004"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"S. Sidiropoulos","raw_affiliation_strings":["Aeluros, Inc., Mountain View, CA, USA","Computer Systems Laboratory, University of Stanford, Stanford, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Aeluros, Inc., Mountain View, CA, USA","institution_ids":[]},{"raw_affiliation_string":"Computer Systems Laboratory, University of Stanford, Stanford, CA, USA","institution_ids":["https://openalex.org/I97018004"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5090469068","display_name":"Mark Horowitz","orcid":"https://orcid.org/0000-0003-3245-7542"},"institutions":[{"id":"https://openalex.org/I97018004","display_name":"Stanford University","ror":"https://ror.org/00f54p054","country_code":"US","type":"education","lineage":["https://openalex.org/I97018004"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"M. Horowitz","raw_affiliation_strings":["Computer Systems Laboratory, University of Stanford, Stanford, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Systems Laboratory, University of Stanford, Stanford, CA, USA","institution_ids":["https://openalex.org/I97018004"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I97018004"],"apc_list":null,"apc_paid":null,"fwci":1.241,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.79618765,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"28","issue":null,"first_page":"375","last_page":"380"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/schematic","display_name":"Schematic","score":0.9090360403060913},{"id":"https://openalex.org/keywords/reuse","display_name":"Reuse","score":0.73099684715271},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6871008276939392},{"id":"https://openalex.org/keywords/representation","display_name":"Representation (politics)","score":0.4925733208656311},{"id":"https://openalex.org/keywords/task","display_name":"Task (project management)","score":0.4434778094291687},{"id":"https://openalex.org/keywords/systems-engineering","display_name":"Systems engineering","score":0.43670016527175903},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.4255751669406891},{"id":"https://openalex.org/keywords/analogue-electronics","display_name":"Analogue electronics","score":0.4228246212005615},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.41329145431518555},{"id":"https://openalex.org/keywords/software-engineering","display_name":"Software engineering","score":0.33479392528533936},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3041938543319702},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.29791995882987976},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.21994605660438538},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.20410960912704468},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.18755361437797546}],"concepts":[{"id":"https://openalex.org/C192328126","wikidata":"https://www.wikidata.org/wiki/Q4514647","display_name":"Schematic","level":2,"score":0.9090360403060913},{"id":"https://openalex.org/C206588197","wikidata":"https://www.wikidata.org/wiki/Q846574","display_name":"Reuse","level":2,"score":0.73099684715271},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6871008276939392},{"id":"https://openalex.org/C2776359362","wikidata":"https://www.wikidata.org/wiki/Q2145286","display_name":"Representation (politics)","level":3,"score":0.4925733208656311},{"id":"https://openalex.org/C2780451532","wikidata":"https://www.wikidata.org/wiki/Q759676","display_name":"Task (project management)","level":2,"score":0.4434778094291687},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.43670016527175903},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.4255751669406891},{"id":"https://openalex.org/C29074008","wikidata":"https://www.wikidata.org/wiki/Q174925","display_name":"Analogue electronics","level":3,"score":0.4228246212005615},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.41329145431518555},{"id":"https://openalex.org/C115903868","wikidata":"https://www.wikidata.org/wiki/Q80993","display_name":"Software engineering","level":1,"score":0.33479392528533936},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3041938543319702},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.29791995882987976},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.21994605660438538},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.20410960912704468},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.18755361437797546},{"id":"https://openalex.org/C548081761","wikidata":"https://www.wikidata.org/wiki/Q180388","display_name":"Waste management","level":1,"score":0.0},{"id":"https://openalex.org/C94625758","wikidata":"https://www.wikidata.org/wiki/Q7163","display_name":"Politics","level":2,"score":0.0},{"id":"https://openalex.org/C17744445","wikidata":"https://www.wikidata.org/wiki/Q36442","display_name":"Political science","level":0,"score":0.0},{"id":"https://openalex.org/C199539241","wikidata":"https://www.wikidata.org/wiki/Q7748","display_name":"Law","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/iccad.2003.1257805","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccad.2003.1257805","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486)","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.377.3134","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.377.3134","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.cs.york.ac.uk/rts/docs/SIGDA-Compendium-1994-2004/papers/2003/iccad03/pdffiles/05c_4.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":34,"referenced_works":["https://openalex.org/W596257947","https://openalex.org/W617071296","https://openalex.org/W1491178396","https://openalex.org/W1527137186","https://openalex.org/W1544623790","https://openalex.org/W1599994156","https://openalex.org/W1602708344","https://openalex.org/W1979564935","https://openalex.org/W1994218207","https://openalex.org/W1999357165","https://openalex.org/W2038038283","https://openalex.org/W2042883481","https://openalex.org/W2047708141","https://openalex.org/W2081754750","https://openalex.org/W2085399494","https://openalex.org/W2100128641","https://openalex.org/W2106476087","https://openalex.org/W2114953806","https://openalex.org/W2115056502","https://openalex.org/W2122919983","https://openalex.org/W2124390946","https://openalex.org/W2132897890","https://openalex.org/W2134342348","https://openalex.org/W2136138043","https://openalex.org/W2141776905","https://openalex.org/W2144133630","https://openalex.org/W2150400017","https://openalex.org/W2162448355","https://openalex.org/W2164116828","https://openalex.org/W2220839306","https://openalex.org/W2280387905","https://openalex.org/W2613359208","https://openalex.org/W4233538641","https://openalex.org/W4285719527"],"related_works":["https://openalex.org/W3154683910","https://openalex.org/W1846734616","https://openalex.org/W2359532622","https://openalex.org/W3134543635","https://openalex.org/W2921318524","https://openalex.org/W2377571686","https://openalex.org/W4380988671","https://openalex.org/W1925657225","https://openalex.org/W2288239609","https://openalex.org/W4395955518"],"abstract_inverted_index":{"Recent":[0],"analog":[1,68],"design":[2,64],"tools":[3],"have":[4],"started":[5],"to":[6,9,27,61],"allow":[7],"designers":[8],"archive":[10],"not":[11],"only":[12],"the":[13,20,23,48,74,78,84,87,102,106,109,114,132,141],"sized":[14],"schematics":[15],"but":[16],"also":[17,82],"some":[18],"of":[19,47,112,136,143],"objectives":[21],"that":[22,41,120],"circuit":[24,50],"is":[25,118],"trying":[26],"achieve.":[28],"This":[29],"paper":[30],"first":[31],"describes":[32,54],"STAR":[33],"(Schematic":[34],"Tool":[35],"for":[36,77,127],"Analog":[37],"Reuse),":[38],"a":[39,121,144],"system":[40,57,103,138],"captures":[42],"designer's":[43],"knowledge":[44],"as":[45],"part":[46],"archival":[49],"representation,":[51],"and":[52,93,134],"then":[53],"how":[55,94],"this":[56,137],"can":[58],"be":[59],"used":[60],"create":[62],"portable":[63,67],"modules.":[65],"Creating":[66],"modules":[69],"require":[70],"more":[71],"than":[72],"just":[73],"optimization":[75],"criteria":[76],"cell.":[79],"It":[80],"must":[81,104],"include":[83],"constraints":[85,96],"on":[86],"cell's":[88],"environment":[89],"(for":[90],"proper":[91],"operation),":[92],"these":[95],"should":[97],"scale":[98],"with":[99],"technology.":[100],"Furthermore,":[101],"help":[105],"designer":[107,122],"in":[108],"current":[110],"task":[111],"creating":[113,125],"design,":[115],"since":[116],"it":[117],"rare":[119],"thinks":[123],"about":[124],"IP":[126],"someone":[128],"else.":[129],"We":[130],"demonstrate":[131],"capability":[133],"utility":[135],"by":[139],"examining":[140],"reuse":[142],"phase-locked":[145],"loop.":[146]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}