{"id":"https://openalex.org/W2121582724","doi":"https://doi.org/10.1109/icc.2005.1494505","title":"Space-memory-memory architecture for CLOS-network packet switches","display_name":"Space-memory-memory architecture for CLOS-network packet switches","publication_year":2005,"publication_date":"2005-01-01","ids":{"openalex":"https://openalex.org/W2121582724","doi":"https://doi.org/10.1109/icc.2005.1494505","mag":"2121582724"},"language":"en","primary_location":{"id":"doi:10.1109/icc.2005.1494505","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icc.2005.1494505","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE International Conference on Communications, 2005. ICC 2005. 2005","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100353959","display_name":"Xin Li","orcid":"https://orcid.org/0000-0002-8474-6330"},"institutions":[{"id":"https://openalex.org/I200769079","display_name":"Hong Kong University of Science and Technology","ror":"https://ror.org/00q4vv597","country_code":"HK","type":"education","lineage":["https://openalex.org/I200769079"]}],"countries":["HK"],"is_corresponding":false,"raw_author_name":"Xin Li","raw_affiliation_strings":["Dept. of Comput. Sci., Hong Kong Univ. of Sci. & Technol., China","[Department of Computer Science, Hong Kong University of Science and Technology, China]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dept. of Comput. Sci., Hong Kong Univ. of Sci. & Technol., China","institution_ids":["https://openalex.org/I200769079"]},{"raw_affiliation_string":"[Department of Computer Science, Hong Kong University of Science and Technology, China]","institution_ids":["https://openalex.org/I200769079"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100733156","display_name":"Zhen Zhou","orcid":"https://orcid.org/0000-0001-5767-4928"},"institutions":[{"id":"https://openalex.org/I200769079","display_name":"Hong Kong University of Science and Technology","ror":"https://ror.org/00q4vv597","country_code":"HK","type":"education","lineage":["https://openalex.org/I200769079"]}],"countries":["HK"],"is_corresponding":false,"raw_author_name":"Zhen Zhou","raw_affiliation_strings":["Dept. of Comput. Sci., Hong Kong Univ. of Sci. & Technol., China","[Department of Computer Science, Hong Kong University of Science and Technology, China]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dept. of Comput. Sci., Hong Kong Univ. of Sci. & Technol., China","institution_ids":["https://openalex.org/I200769079"]},{"raw_affiliation_string":"[Department of Computer Science, Hong Kong University of Science and Technology, China]","institution_ids":["https://openalex.org/I200769079"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5001299811","display_name":"Mounir Hamdi","orcid":"https://orcid.org/0000-0002-9766-0085"},"institutions":[{"id":"https://openalex.org/I200769079","display_name":"Hong Kong University of Science and Technology","ror":"https://ror.org/00q4vv597","country_code":"HK","type":"education","lineage":["https://openalex.org/I200769079"]}],"countries":["HK"],"is_corresponding":false,"raw_author_name":"M. Hamdi","raw_affiliation_strings":["Dept. of Comput. Sci., Hong Kong Univ. of Sci. & Technol., China","[Department of Computer Science, Hong Kong University of Science and Technology, China]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dept. of Comput. Sci., Hong Kong Univ. of Sci. & Technol., China","institution_ids":["https://openalex.org/I200769079"]},{"raw_affiliation_string":"[Department of Computer Science, Hong Kong University of Science and Technology, China]","institution_ids":["https://openalex.org/I200769079"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I200769079"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":38,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1031","last_page":"1035 Vol. 2"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12042","display_name":"Satellite Communication Systems","score":0.9907000064849854,"subfield":{"id":"https://openalex.org/subfields/2202","display_name":"Aerospace Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9807999730110168,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8411312103271484},{"id":"https://openalex.org/keywords/clos-network","display_name":"Clos network","score":0.8141509294509888},{"id":"https://openalex.org/keywords/memory-architecture","display_name":"Memory architecture","score":0.5511536002159119},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.526995837688446},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.49882984161376953},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.4973032772541046},{"id":"https://openalex.org/keywords/cache-only-memory-architecture","display_name":"Cache-only memory architecture","score":0.48321473598480225},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.48022016882896423},{"id":"https://openalex.org/keywords/network-packet","display_name":"Network packet","score":0.47994449734687805},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.4393139183521271},{"id":"https://openalex.org/keywords/queueing-theory","display_name":"Queueing theory","score":0.4278199076652527},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.40283894538879395},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.3781486749649048},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3688540458679199},{"id":"https://openalex.org/keywords/uniform-memory-access","display_name":"Uniform memory access","score":0.36735427379608154},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.18951115012168884},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.16329333186149597},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.13347432017326355}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8411312103271484},{"id":"https://openalex.org/C119700423","wikidata":"https://www.wikidata.org/wiki/Q4418086","display_name":"Clos network","level":2,"score":0.8141509294509888},{"id":"https://openalex.org/C2779602883","wikidata":"https://www.wikidata.org/wiki/Q15544750","display_name":"Memory architecture","level":2,"score":0.5511536002159119},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.526995837688446},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.49882984161376953},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.4973032772541046},{"id":"https://openalex.org/C3720319","wikidata":"https://www.wikidata.org/wiki/Q5015937","display_name":"Cache-only memory architecture","level":5,"score":0.48321473598480225},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.48022016882896423},{"id":"https://openalex.org/C158379750","wikidata":"https://www.wikidata.org/wiki/Q214111","display_name":"Network packet","level":2,"score":0.47994449734687805},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.4393139183521271},{"id":"https://openalex.org/C22684755","wikidata":"https://www.wikidata.org/wiki/Q847526","display_name":"Queueing theory","level":2,"score":0.4278199076652527},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.40283894538879395},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.3781486749649048},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3688540458679199},{"id":"https://openalex.org/C51290061","wikidata":"https://www.wikidata.org/wiki/Q1936765","display_name":"Uniform memory access","level":4,"score":0.36735427379608154},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.18951115012168884},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.16329333186149597},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.13347432017326355},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/icc.2005.1494505","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icc.2005.1494505","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE International Conference on Communications, 2005. ICC 2005. 2005","raw_type":"proceedings-article"},{"id":"pmh:oai:repository.hkust.edu.hk:1783.1-47984","is_oa":false,"landing_page_url":"http://repository.hkust.edu.hk/ir/Record/1783.1-47984","pdf_url":null,"source":{"id":"https://openalex.org/S4306401796","display_name":"Rare & Special e-Zone (The Hong Kong University of Science and Technology)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I200769079","host_organization_name":"Hong Kong University of Science and Technology","host_organization_lineage":["https://openalex.org/I200769079"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Conference paper"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.44999998807907104,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W1504678909","https://openalex.org/W2083924510","https://openalex.org/W2096313289","https://openalex.org/W2134316164","https://openalex.org/W2152530926","https://openalex.org/W2164312797","https://openalex.org/W2165664455","https://openalex.org/W6630035545"],"related_works":["https://openalex.org/W254684032","https://openalex.org/W1848192231","https://openalex.org/W1974211070","https://openalex.org/W2934889147","https://openalex.org/W1942416056","https://openalex.org/W2143690511","https://openalex.org/W1591576069","https://openalex.org/W4281569059","https://openalex.org/W1975698617","https://openalex.org/W2043352873"],"abstract_inverted_index":{"A":[0],"Clos-network":[1],"architecture":[2,138,147,155,190,203],"is":[3,68,191,210],"an":[4],"attractive":[5],"alternative":[6],"for":[7,80,186],"constructing":[8],"scalable":[9],"packet":[10],"switches":[11],"because":[12],"of":[13,113],"its":[14,31],"distributed":[15],"and":[16,42,124,209],"modular":[17],"design.":[18],"It":[19],"can":[20,204],"be":[21,129],"classified":[22],"according":[23],"to":[24,85,98,160,192],"different":[25],"buffer":[26],"(memory)":[27],"allocation":[28],"schemes":[29,62],"in":[30,179],"switching":[32],"stages.":[33],"The":[34,103,145,183],"most":[35],"studied":[36],"architectures":[37,53,82],"are":[38,177],"the":[39,43,65,101,126,153,180,187,201],"space-space-space":[40],"(S3)":[41],"memory-space-memory":[44],"(MSM)":[45],"architectures.":[46],"This":[47],"paper":[48,132],"shows":[49],"that":[50,139,172],"these":[51,81,122],"two":[52],"cannot":[54],"achieve":[55,161,205],"efficient":[56],"throughput":[57,163],"with":[58],"conventional":[59],"random":[60],"dispatching":[61],"even":[63],"if":[64],"fabric":[66],"itself":[67],"non-blocking.":[69],"Previous":[70],"research":[71],"hence":[72],"has":[73,148],"focused":[74],"on":[75],"developing":[76],"intelligent":[77],"scheduling":[78],"algorithms":[79],"so":[83],"as":[84,152],"improve":[86],"their":[87],"throughput.":[88],"However,":[89],"we":[90,96],"face":[91],"various":[92],"challenging":[93],"problems":[94,104,123],"when":[95],"try":[97],"actually":[99],"implement":[100],"algorithms.":[102],"include":[105],"performance":[106],"degradation":[107],"under":[108,164],"constrained":[109],"arbitration":[110],"time,":[111],"needs":[112],"centralized":[114],"or":[115],"complex":[116],"scheduler":[117],"hardware,":[118],"etc.":[119],"To":[120],"solve":[121],"at":[125],"same":[127],"time":[128],"practical,":[130],"this":[131],"proposes":[133],"a":[134,199],"novel":[135],"space-memory-memory":[136],"(SMM)":[137],"does":[140],"not":[141],"need":[142],"any":[143,165],"schedulers.":[144],"SMM":[146,189,202],"similar":[149],"hardware":[150],"complexity":[151],"MSM":[154],"has,":[156],"while":[157],"been":[158],"proven":[159],"100%":[162],"admissible":[166],"traffic.":[167],"Our":[168],"queuing":[169],"analysis":[170],"demonstrates":[171],"only":[173,184],"small":[174,194],"size":[175],"buffers":[176],"needed":[178],"central":[181],"stage.":[182],"tradeoff":[185],"proposed":[188],"employ":[193],"extra":[195],"resequencing":[196],"buffers.":[197],"As":[198],"result,":[200],"very":[206],"high":[207],"performance,":[208],"readily":[211],"implemented":[212],"using":[213],"current":[214],"technology.":[215]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":3},{"year":2017,"cited_by_count":4},{"year":2016,"cited_by_count":5},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":4},{"year":2012,"cited_by_count":4}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}