{"id":"https://openalex.org/W2112745000","doi":"https://doi.org/10.1109/icat.2009.5348448","title":"Design and implementation of an IP-core based safety-related communication architecture on FPGA","display_name":"Design and implementation of an IP-core based safety-related communication architecture on FPGA","publication_year":2009,"publication_date":"2009-10-01","ids":{"openalex":"https://openalex.org/W2112745000","doi":"https://doi.org/10.1109/icat.2009.5348448","mag":"2112745000"},"language":"en","primary_location":{"id":"doi:10.1109/icat.2009.5348448","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icat.2009.5348448","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 XXII International Symposium on Information, Communication and Automation Technologies","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5005437316","display_name":"Josef B\u00f6rcs\u00f6k","orcid":"https://orcid.org/0000-0003-4394-1305"},"institutions":[{"id":"https://openalex.org/I106157433","display_name":"University of Kassel","ror":"https://ror.org/04zc7p361","country_code":"DE","type":"education","lineage":["https://openalex.org/I106157433"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Josef Borcsok","raw_affiliation_strings":["University of Kassel, Germany","Chair for Computer Architecture and System Programming, University of Kassel, Germany"],"affiliations":[{"raw_affiliation_string":"University of Kassel, Germany","institution_ids":["https://openalex.org/I106157433"]},{"raw_affiliation_string":"Chair for Computer Architecture and System Programming, University of Kassel, Germany","institution_ids":["https://openalex.org/I106157433"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5002287165","display_name":"Ali Hayek","orcid":null},"institutions":[{"id":"https://openalex.org/I106157433","display_name":"University of Kassel","ror":"https://ror.org/04zc7p361","country_code":"DE","type":"education","lineage":["https://openalex.org/I106157433"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Ali Hayek","raw_affiliation_strings":["University of Kassel, Germany","Chair for Computer Architecture and System Programming, University of Kassel, Germany"],"affiliations":[{"raw_affiliation_string":"University of Kassel, Germany","institution_ids":["https://openalex.org/I106157433"]},{"raw_affiliation_string":"Chair for Computer Architecture and System Programming, University of Kassel, Germany","institution_ids":["https://openalex.org/I106157433"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5020890403","display_name":"Bashier Machmur","orcid":null},"institutions":[{"id":"https://openalex.org/I106157433","display_name":"University of Kassel","ror":"https://ror.org/04zc7p361","country_code":"DE","type":"education","lineage":["https://openalex.org/I106157433"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Bashier Machmur","raw_affiliation_strings":["University of Kassel, Germany","Chair for Computer Architecture and System Programming, University of Kassel, Germany"],"affiliations":[{"raw_affiliation_string":"University of Kassel, Germany","institution_ids":["https://openalex.org/I106157433"]},{"raw_affiliation_string":"Chair for Computer Architecture and System Programming, University of Kassel, Germany","institution_ids":["https://openalex.org/I106157433"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101745975","display_name":"Muhammad Umar","orcid":"https://orcid.org/0000-0001-7460-1341"},"institutions":[{"id":"https://openalex.org/I106157433","display_name":"University of Kassel","ror":"https://ror.org/04zc7p361","country_code":"DE","type":"education","lineage":["https://openalex.org/I106157433"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Muhammad Umar","raw_affiliation_strings":["University of Kassel, Germany","Chair for Computer Architecture and System Programming, University of Kassel, Germany"],"affiliations":[{"raw_affiliation_string":"University of Kassel, Germany","institution_ids":["https://openalex.org/I106157433"]},{"raw_affiliation_string":"Chair for Computer Architecture and System Programming, University of Kassel, Germany","institution_ids":["https://openalex.org/I106157433"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5005437316"],"corresponding_institution_ids":["https://openalex.org/I106157433"],"apc_list":null,"apc_paid":null,"fwci":1.0553,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.78293044,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7909519672393799},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.7448248863220215},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7185332775115967},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.7108021974563599},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.6041402816772461},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5767146944999695},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.5335104465484619},{"id":"https://openalex.org/keywords/reduced-instruction-set-computing","display_name":"Reduced instruction set computing","score":0.4760829508304596},{"id":"https://openalex.org/keywords/simple","display_name":"Simple (philosophy)","score":0.43353337049484253},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2936092019081116},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.2627287805080414}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7909519672393799},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.7448248863220215},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7185332775115967},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.7108021974563599},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.6041402816772461},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5767146944999695},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.5335104465484619},{"id":"https://openalex.org/C126298526","wikidata":"https://www.wikidata.org/wiki/Q189376","display_name":"Reduced instruction set computing","level":3,"score":0.4760829508304596},{"id":"https://openalex.org/C2780586882","wikidata":"https://www.wikidata.org/wiki/Q7520643","display_name":"Simple (philosophy)","level":2,"score":0.43353337049484253},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2936092019081116},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.2627287805080414},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C111472728","wikidata":"https://www.wikidata.org/wiki/Q9471","display_name":"Epistemology","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icat.2009.5348448","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icat.2009.5348448","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 XXII International Symposium on Information, Communication and Automation Technologies","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5199999809265137,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W654063854","https://openalex.org/W1585327475","https://openalex.org/W2127159302","https://openalex.org/W2154727547","https://openalex.org/W2161568293","https://openalex.org/W3139593476","https://openalex.org/W6683816381"],"related_works":["https://openalex.org/W3004362061","https://openalex.org/W2364622490","https://openalex.org/W2042515040","https://openalex.org/W2383986884","https://openalex.org/W2356141508","https://openalex.org/W4297665406","https://openalex.org/W2749962643","https://openalex.org/W2101296662","https://openalex.org/W2390807153","https://openalex.org/W1947925516"],"abstract_inverted_index":{"Nowadays":[0],"embedded":[1],"systems":[2],"are":[3,16,88,116],"increasingly":[4],"used":[5,18],"in":[6,19,22,69],"industrial":[7],"applications.":[8],"On":[9],"the":[10,33,37,49,52,77,81,91,95,97,100,104],"other":[11],"hand,":[12],"Intellectual":[13],"Properties":[14],"ldquoIPsrdquo":[15],"being":[17],"complex":[20],"roles":[21],"such":[23,111],"systems.":[24],"The":[25],"purpose":[26],"of":[27,39,55,85,94,99,103],"this":[28],"paper":[29],"is":[30,74],"to":[31],"present":[32],"basic":[34],"ideas":[35],"behind":[36],"building":[38],"an":[40],"IP-based":[41,58],"safety-related":[42],"1oo2":[43,82,105],"architecture":[44,87,107],"on":[45,72],"FPGA":[46],"platform.":[47],"In":[48,90],"first":[50],"part":[51,93],"complete":[53],"design":[54,68],"a":[56,64,113],"simple":[57],"8":[59],"bit":[60],"RISC":[61],"processor":[62],"and":[63,76,102,108],"system":[65],"on-chip":[66],"(SoC)":[67],"synthesizable":[70],"VHDL":[71],"FPGA-platform":[73],"presented":[75],"safety":[78],"parameters":[79],"for":[80],"(one":[83],"out":[84],"two)":[86],"given.":[89],"second":[92],"paper,":[96],"implementation":[98],"single":[101],"communication":[106],"some":[109],"results":[110],"as":[112],"running":[114],"application":[115],"shown.":[117]},"counts_by_year":[{"year":2013,"cited_by_count":2},{"year":2012,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
