{"id":"https://openalex.org/W2403734471","doi":"https://doi.org/10.1109/icassp.2016.7472938","title":"Error-resilient sequential cells with successive time borrowing for stochastic computing","display_name":"Error-resilient sequential cells with successive time borrowing for stochastic computing","publication_year":2016,"publication_date":"2016-03-01","ids":{"openalex":"https://openalex.org/W2403734471","doi":"https://doi.org/10.1109/icassp.2016.7472938","mag":"2403734471"},"language":"en","primary_location":{"id":"doi:10.1109/icassp.2016.7472938","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icassp.2016.7472938","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5005949927","display_name":"Wei-Chang Liu","orcid":null},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Wei-Chang Liu","raw_affiliation_strings":["Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5043383517","display_name":"Ching-Da Chan","orcid":null},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Ching-Da Chan","raw_affiliation_strings":["Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5074141198","display_name":"Shuo-An Huang","orcid":"https://orcid.org/0000-0001-8121-0242"},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Shuo-An Huang","raw_affiliation_strings":["Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5037928465","display_name":"Chi-Wei Lo","orcid":null},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Chi-Wei Lo","raw_affiliation_strings":["Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101750729","display_name":"Chia\u2010Hsiang Yang","orcid":"https://orcid.org/0000-0003-1163-321X"},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Chia-Hsiang Yang","raw_affiliation_strings":["Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5061859062","display_name":"Shyh\u2010Jye Jou","orcid":"https://orcid.org/0000-0002-8821-3486"},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Shyh-Jye Jou","raw_affiliation_strings":["Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.03764371,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"6545","last_page":"6549"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/stochastic-computing","display_name":"Stochastic computing","score":0.7280207872390747},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7077203989028931},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.5722190737724304},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.5693642497062683},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.5027892589569092},{"id":"https://openalex.org/keywords/feed-forward","display_name":"Feed forward","score":0.47888845205307007},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.4578685760498047},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.44648152589797974},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.35252147912979126},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.29833680391311646},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.2938200831413269},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2916993498802185},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.26194441318511963},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.13029295206069946},{"id":"https://openalex.org/keywords/control-engineering","display_name":"Control engineering","score":0.10658827424049377}],"concepts":[{"id":"https://openalex.org/C2780971903","wikidata":"https://www.wikidata.org/wiki/Q2933705","display_name":"Stochastic computing","level":3,"score":0.7280207872390747},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7077203989028931},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.5722190737724304},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.5693642497062683},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.5027892589569092},{"id":"https://openalex.org/C38858127","wikidata":"https://www.wikidata.org/wiki/Q5441228","display_name":"Feed forward","level":2,"score":0.47888845205307007},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.4578685760498047},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.44648152589797974},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.35252147912979126},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.29833680391311646},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.2938200831413269},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2916993498802185},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.26194441318511963},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.13029295206069946},{"id":"https://openalex.org/C133731056","wikidata":"https://www.wikidata.org/wiki/Q4917288","display_name":"Control engineering","level":1,"score":0.10658827424049377},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icassp.2016.7472938","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icassp.2016.7472938","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1554898868","https://openalex.org/W2015710739","https://openalex.org/W2039559700","https://openalex.org/W2048874455","https://openalex.org/W2102986659","https://openalex.org/W2104677471","https://openalex.org/W2107766185","https://openalex.org/W2117648153","https://openalex.org/W2123262270","https://openalex.org/W2151802820","https://openalex.org/W2156667996","https://openalex.org/W2296253867","https://openalex.org/W4236432903","https://openalex.org/W6660155203","https://openalex.org/W6682165497"],"related_works":["https://openalex.org/W2800155864","https://openalex.org/W2955267291","https://openalex.org/W2770413419","https://openalex.org/W4200623496","https://openalex.org/W2286391053","https://openalex.org/W2294708870","https://openalex.org/W4322624379","https://openalex.org/W2982600058","https://openalex.org/W1963486701","https://openalex.org/W2614944750"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"error-resilient":[3],"sequential":[4,72],"building":[5,99],"blocks":[6,100],"with":[7,77,96],"time-borrowing":[8],"capability":[9],"without":[10,52],"extra":[11],"latches":[12],"and":[13,68,86],"generated":[14],"clocks.":[15],"The":[16,59,70,104],"circuits":[17],"are":[18,74],"able":[19],"to":[20,34,65],"recover":[21],"the":[22,41,108,111,119],"timing":[23,42],"errors":[24,43],"caused":[25],"by":[26,32,116],"PVT":[27],"variations":[28],"and/or":[29],"over-voltage":[30],"scaling":[31],"up":[33],"half":[35],"a":[36,56,90,94,124],"cycle.":[37],"Unlike":[38],"prior":[39],"works,":[40],"can":[44,62],"be":[45,63],"recovered":[46],"dynamically":[47],"through":[48],"successive":[49],"time":[50],"borrowing":[51],"stalled":[53],"cycles,":[54],"retaining":[55],"constant":[57],"throughput.":[58],"circuit":[60],"structure":[61],"applied":[64],"both":[66,84],"ASICs":[67],"microprocessors.":[69],"proposed":[71],"cells":[73],"highly":[75],"compatible":[76],"current":[78],"cell-based":[79],"IC":[80],"design":[81,95],"flow,":[82],"for":[83,127],"feedforward":[85],"feedback":[87],"datapaths.":[88],"As":[89],"proof":[91],"of":[92,110],"concept,":[93],"key":[97],"DSP":[98,112],"has":[101],"been":[102],"verified.":[103],"results":[105],"show":[106],"that":[107],"performance":[109],"modules":[113],"is":[114],"improved":[115],"13-15%":[117],"in":[118],"worst-case":[120],"operation":[121,133],"condition,":[122],"yielding":[123],"promising":[125],"solution":[126],"stochastic":[128],"computing":[129],"under":[130],"an":[131],"unreliable":[132],"condition.":[134]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
