{"id":"https://openalex.org/W2142570900","doi":"https://doi.org/10.1109/icassp.2002.5745322","title":"Design space exploration for DSP applications using the ASIP development system PEAS-III","display_name":"Design space exploration for DSP applications using the ASIP development system PEAS-III","publication_year":2002,"publication_date":"2002-05-01","ids":{"openalex":"https://openalex.org/W2142570900","doi":"https://doi.org/10.1109/icassp.2002.5745322","mag":"2142570900"},"language":"en","primary_location":{"id":"doi:10.1109/icassp.2002.5745322","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icassp.2002.5745322","pdf_url":null,"source":{"id":"https://openalex.org/S4363607879","display_name":"IEEE International Conference on Acoustics Speech and Signal Processing","issn_l":"1520-6149","issn":["1520-6149","2379-190X"],"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE International Conference on Acoustics Speech and Signal Processing","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5032229041","display_name":"Shinsuke Kobayashi","orcid":null},"institutions":[{"id":"https://openalex.org/I98285908","display_name":"The University of Osaka","ror":"https://ror.org/035t8zc32","country_code":"JP","type":"education","lineage":["https://openalex.org/I98285908"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Shinsuke Kobayashi","raw_affiliation_strings":["Department of Informatics and Mathematical Science, Osaka University, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Informatics and Mathematical Science, Osaka University, Japan","institution_ids":["https://openalex.org/I98285908"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5048120314","display_name":"Kentaro Mita","orcid":null},"institutions":[{"id":"https://openalex.org/I98285908","display_name":"The University of Osaka","ror":"https://ror.org/035t8zc32","country_code":"JP","type":"education","lineage":["https://openalex.org/I98285908"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Kentaro Mita","raw_affiliation_strings":["Department of Informatics and Mathematical Science, Osaka University, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Informatics and Mathematical Science, Osaka University, Japan","institution_ids":["https://openalex.org/I98285908"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101432602","display_name":"Yoshinori Takeuchi","orcid":"https://orcid.org/0000-0001-6936-3596"},"institutions":[{"id":"https://openalex.org/I98285908","display_name":"The University of Osaka","ror":"https://ror.org/035t8zc32","country_code":"JP","type":"education","lineage":["https://openalex.org/I98285908"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Yoshinori Takeuchi","raw_affiliation_strings":["Department of Informatics and Mathematical Science, Osaka University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Informatics and Mathematical Science, Osaka University","institution_ids":["https://openalex.org/I98285908"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5109865597","display_name":"Masaharu Imai","orcid":null},"institutions":[{"id":"https://openalex.org/I98285908","display_name":"The University of Osaka","ror":"https://ror.org/035t8zc32","country_code":"JP","type":"education","lineage":["https://openalex.org/I98285908"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Masaharu Imai","raw_affiliation_strings":["Department of Informatics and Mathematical Science, Osaka University, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Informatics and Mathematical Science, Osaka University, Japan","institution_ids":["https://openalex.org/I98285908"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I98285908"],"apc_list":null,"apc_paid":null,"fwci":1.7181,"has_fulltext":false,"cited_by_count":15,"citation_normalized_percentile":{"value":0.84993973,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"III","last_page":"3168"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9965000152587891,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12810","display_name":"Real-time simulation and control systems","score":0.9951000213623047,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.8969129920005798},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8170779943466187},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.6980904936790466},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.5681940317153931},{"id":"https://openalex.org/keywords/digital-signal-processor","display_name":"Digital signal processor","score":0.5425707697868347},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5165385603904724},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.47413182258605957},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.4639214277267456},{"id":"https://openalex.org/keywords/texas-instruments-davinci","display_name":"Texas Instruments DaVinci","score":0.43275386095046997},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4308268129825592},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.324582576751709},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.14050328731536865},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.13676640391349792}],"concepts":[{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.8969129920005798},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8170779943466187},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.6980904936790466},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.5681940317153931},{"id":"https://openalex.org/C161611012","wikidata":"https://www.wikidata.org/wiki/Q106370","display_name":"Digital signal processor","level":3,"score":0.5425707697868347},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5165385603904724},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.47413182258605957},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.4639214277267456},{"id":"https://openalex.org/C45549533","wikidata":"https://www.wikidata.org/wiki/Q7707766","display_name":"Texas Instruments DaVinci","level":4,"score":0.43275386095046997},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4308268129825592},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.324582576751709},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.14050328731536865},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.13676640391349792}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icassp.2002.5745322","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icassp.2002.5745322","pdf_url":null,"source":{"id":"https://openalex.org/S4363607879","display_name":"IEEE International Conference on Acoustics Speech and Signal Processing","issn_l":"1520-6149","issn":["1520-6149","2379-190X"],"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE International Conference on Acoustics Speech and Signal Processing","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.550000011920929,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W1501834527","https://openalex.org/W1568871614","https://openalex.org/W1612189975","https://openalex.org/W1954375898","https://openalex.org/W1981305988","https://openalex.org/W2010074783"],"related_works":["https://openalex.org/W2390600871","https://openalex.org/W2379610108","https://openalex.org/W2319687164","https://openalex.org/W2373806376","https://openalex.org/W2348897940","https://openalex.org/W2616811039","https://openalex.org/W2167555800","https://openalex.org/W2077289773","https://openalex.org/W2356465519","https://openalex.org/W1927072911"],"abstract_inverted_index":{"This":[0],"paper":[1],"describes":[2],"rapid":[3],"design":[4,132],"space":[5],"exploration":[6],"for":[7,21,56,113],"DSP":[8],"applications":[9,92,118],"using":[10,135],"the":[11,36,40,51,57,62,66,71,105,125,131],"PEAS-III":[12,41,67],"system,":[13,42,68],"which":[14,32,85],"is":[15,33,43,48,86],"a":[16,28],"configurable":[17],"processor":[18,72,127],"development":[19],"environment":[20],"application":[22],"domain":[23],"specific":[24],"embedded":[25],"systems.":[26],"First,":[27],"compiler":[29,47,79],"generation":[30,60],"method,":[31],"one":[34],"of":[35,61,91,111],"key":[37],"technologies":[38],"in":[39,121],"proposed.":[44],"The":[45],"target":[46,63,78],"generated":[49,94,136],"from":[50,88],"same":[52],"information":[53],"as":[54],"used":[55],"synthesizable":[58],"HDL":[59,73],"processor.":[64],"Using":[65],"not":[69],"only":[70],"description":[74],"but":[75],"also":[76],"its":[77],"are":[80],"generated.":[81],"Therefore,":[82],"execution":[83,89],"time":[84],"computed":[87],"cycles":[90],"and":[93,109,115,124,138],"processor's":[95],"frequency":[96],"can":[97],"be":[98],"rapidly":[99],"evaluated.":[100],"Experimental":[101],"results":[102],"showed":[103],"that":[104],"trade-offs":[106],"between":[107],"area":[108],"performance":[110],"processors":[112],"DCT":[114],"FIR":[116],"filter":[117],"were":[119],"analyzed":[120],"4.1":[122],"hours":[123],"optimal":[126],"was":[128],"selected":[129],"under":[130],"constraint":[133],"by":[134],"compilers":[137],"processors.":[139]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}