{"id":"https://openalex.org/W2135865344","doi":"https://doi.org/10.1109/icassp.1998.678196","title":"Multimedia applications of microprocessor with embedded DRAM","display_name":"Multimedia applications of microprocessor with embedded DRAM","publication_year":2002,"publication_date":"2002-11-27","ids":{"openalex":"https://openalex.org/W2135865344","doi":"https://doi.org/10.1109/icassp.1998.678196","mag":"2135865344"},"language":"en","primary_location":{"id":"doi:10.1109/icassp.1998.678196","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icassp.1998.678196","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 1998 IEEE International Conference on Acoustics, Speech and Signal Processing, ICASSP '98 (Cat. No.98CH36181)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5067052913","display_name":"Yasuhiro Nunomura","orcid":null},"institutions":[{"id":"https://openalex.org/I1306287861","display_name":"Mitsubishi Group (Japan)","ror":"https://ror.org/0234cd281","country_code":"JP","type":"company","lineage":["https://openalex.org/I1306287861"]},{"id":"https://openalex.org/I4210133125","display_name":"Mitsubishi Electric (Japan)","ror":"https://ror.org/033y26782","country_code":"JP","type":"company","lineage":["https://openalex.org/I1306287861","https://openalex.org/I4210133125"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Y. Nunomura","raw_affiliation_strings":["System LSI Laboratory, Mitsubishi Electric Corporation Limited, Itami, Hyogo, Japan","Syst. LSI Lab., Mitsubishi Electr. Corp., Hyogo, Japan"],"affiliations":[{"raw_affiliation_string":"System LSI Laboratory, Mitsubishi Electric Corporation Limited, Itami, Hyogo, Japan","institution_ids":["https://openalex.org/I4210133125"]},{"raw_affiliation_string":"Syst. LSI Lab., Mitsubishi Electr. Corp., Hyogo, Japan","institution_ids":["https://openalex.org/I1306287861"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5014507741","display_name":"Toshiyuki Shimizu","orcid":"https://orcid.org/0000-0002-0547-8922"},"institutions":[{"id":"https://openalex.org/I39854257","display_name":"Mitsubishi Electric (Germany)","ror":"https://ror.org/04ccqwj03","country_code":"DE","type":"company","lineage":["https://openalex.org/I1306287861","https://openalex.org/I39854257","https://openalex.org/I4210133125"]},{"id":"https://openalex.org/I4210133125","display_name":"Mitsubishi Electric (Japan)","ror":"https://ror.org/033y26782","country_code":"JP","type":"company","lineage":["https://openalex.org/I1306287861","https://openalex.org/I4210133125"]}],"countries":["DE","JP"],"is_corresponding":false,"raw_author_name":"T. Shimizu","raw_affiliation_strings":["System LSI Laboratory, Mitsubishi Electric Corporation Limited, Itami, Hyogo, Japan","[System LSI Laboratory, Mitsubishi Electric Corporation Limited, Itami, Hyogo, Japan]"],"affiliations":[{"raw_affiliation_string":"System LSI Laboratory, Mitsubishi Electric Corporation Limited, Itami, Hyogo, Japan","institution_ids":["https://openalex.org/I4210133125"]},{"raw_affiliation_string":"[System LSI Laboratory, Mitsubishi Electric Corporation Limited, Itami, Hyogo, Japan]","institution_ids":["https://openalex.org/I39854257"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110157104","display_name":"Kazunori Saitoh","orcid":null},"institutions":[{"id":"https://openalex.org/I39854257","display_name":"Mitsubishi Electric (Germany)","ror":"https://ror.org/04ccqwj03","country_code":"DE","type":"company","lineage":["https://openalex.org/I1306287861","https://openalex.org/I39854257","https://openalex.org/I4210133125"]},{"id":"https://openalex.org/I4210133125","display_name":"Mitsubishi Electric (Japan)","ror":"https://ror.org/033y26782","country_code":"JP","type":"company","lineage":["https://openalex.org/I1306287861","https://openalex.org/I4210133125"]}],"countries":["DE","JP"],"is_corresponding":false,"raw_author_name":"K. Saitoh","raw_affiliation_strings":["System LSI Laboratory, Mitsubishi Electric Corporation Limited, Itami, Hyogo, Japan","[System LSI Laboratory, Mitsubishi Electric Corporation Limited, Itami, Hyogo, Japan]"],"affiliations":[{"raw_affiliation_string":"System LSI Laboratory, Mitsubishi Electric Corporation Limited, Itami, Hyogo, Japan","institution_ids":["https://openalex.org/I4210133125"]},{"raw_affiliation_string":"[System LSI Laboratory, Mitsubishi Electric Corporation Limited, Itami, Hyogo, Japan]","institution_ids":["https://openalex.org/I39854257"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5048268422","display_name":"K. Tsuchihashi","orcid":null},"institutions":[{"id":"https://openalex.org/I4210133125","display_name":"Mitsubishi Electric (Japan)","ror":"https://ror.org/033y26782","country_code":"JP","type":"company","lineage":["https://openalex.org/I1306287861","https://openalex.org/I4210133125"]},{"id":"https://openalex.org/I39854257","display_name":"Mitsubishi Electric (Germany)","ror":"https://ror.org/04ccqwj03","country_code":"DE","type":"company","lineage":["https://openalex.org/I1306287861","https://openalex.org/I39854257","https://openalex.org/I4210133125"]}],"countries":["DE","JP"],"is_corresponding":false,"raw_author_name":"K. Tsuchihashi","raw_affiliation_strings":["System LSI Laboratory, Mitsubishi Electric Corporation Limited, Itami, Hyogo, Japan","[System LSI Laboratory, Mitsubishi Electric Corporation Limited, Itami, Hyogo, Japan]"],"affiliations":[{"raw_affiliation_string":"System LSI Laboratory, Mitsubishi Electric Corporation Limited, Itami, Hyogo, Japan","institution_ids":["https://openalex.org/I4210133125"]},{"raw_affiliation_string":"[System LSI Laboratory, Mitsubishi Electric Corporation Limited, Itami, Hyogo, Japan]","institution_ids":["https://openalex.org/I39854257"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5067052913"],"corresponding_institution_ids":["https://openalex.org/I1306287861","https://openalex.org/I4210133125"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.19410625,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"5","issue":null,"first_page":"3157","last_page":"3160"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10901","display_name":"Advanced Data Compression Techniques","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10901","display_name":"Advanced Data Compression Techniques","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10741","display_name":"Video Coding and Compression Technologies","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7382413744926453},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6504243612289429},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.6242208480834961},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.5854583382606506},{"id":"https://openalex.org/keywords/microprocessor","display_name":"Microprocessor","score":0.5776391625404358},{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.5557248592376709},{"id":"https://openalex.org/keywords/32-bit","display_name":"32-bit","score":0.5287014245986938},{"id":"https://openalex.org/keywords/reduced-instruction-set-computing","display_name":"Reduced instruction set computing","score":0.5227815508842468},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.48445820808410645},{"id":"https://openalex.org/keywords/cas-latency","display_name":"CAS latency","score":0.44155213236808777},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.43363338708877563},{"id":"https://openalex.org/keywords/system-bus","display_name":"System bus","score":0.4293113648891449},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.41176143288612366},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.389238178730011},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.19961562752723694},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.19896990060806274}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7382413744926453},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6504243612289429},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.6242208480834961},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.5854583382606506},{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.5776391625404358},{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.5557248592376709},{"id":"https://openalex.org/C75695347","wikidata":"https://www.wikidata.org/wiki/Q225147","display_name":"32-bit","level":2,"score":0.5287014245986938},{"id":"https://openalex.org/C126298526","wikidata":"https://www.wikidata.org/wiki/Q189376","display_name":"Reduced instruction set computing","level":3,"score":0.5227815508842468},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.48445820808410645},{"id":"https://openalex.org/C189930140","wikidata":"https://www.wikidata.org/wiki/Q1112878","display_name":"CAS latency","level":4,"score":0.44155213236808777},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.43363338708877563},{"id":"https://openalex.org/C136321198","wikidata":"https://www.wikidata.org/wiki/Q2377054","display_name":"System bus","level":2,"score":0.4293113648891449},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.41176143288612366},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.389238178730011},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.19961562752723694},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.19896990060806274},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icassp.1998.678196","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icassp.1998.678196","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 1998 IEEE International Conference on Acoustics, Speech and Signal Processing, ICASSP '98 (Cat. No.98CH36181)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8299999833106995,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":4,"referenced_works":["https://openalex.org/W1599150801","https://openalex.org/W2102843387","https://openalex.org/W2107729468","https://openalex.org/W6635653420"],"related_works":["https://openalex.org/W2082939521","https://openalex.org/W2547220881","https://openalex.org/W3089341786","https://openalex.org/W2532617734","https://openalex.org/W1603816627","https://openalex.org/W2132401245","https://openalex.org/W2056138949","https://openalex.org/W1976244802","https://openalex.org/W2023569851","https://openalex.org/W2389333520"],"abstract_inverted_index":{"The":[0,37,59],"M32R/D":[1,94],"is":[2,61],"a":[3,7,14,18,34,46,66,82,106,114],"32-bit":[4,15],"microprocessor":[5],"with":[6,65,67,77,117],"large-capacity":[8],"on-chip":[9],"DRAM.":[10],"It":[11],"consists":[12],"of":[13,63,69],"RISC":[16],"CPU,":[17,38],"32-bit/spl":[19],"times/16-bit":[20],"multiply":[21],"and":[22,33,40,55,71,100,124],"accumulator":[23],"(MAC),":[24],"either":[25],"1-Mbyte":[26],"or":[27],"2-Mbyte":[28],"DRAM,":[29,39],"4-Kbyte":[30],"cache":[31,41],"memory,":[32],"memory":[35,42],"controller.":[36],"are":[43,128],"connected":[44],"via":[45],"128-bit":[47],"66.6":[48],"MHz":[49],"internal":[50],"bus":[51],"yielding":[52],"high":[53],"performance":[54],"low":[56],"power":[57],"dissipation.":[58],"chip":[60],"capable":[62],"coping":[64],"range":[68],"applications":[70],"thus":[72],"provides":[73],"the":[74],"system":[75,85,108],"designer":[76],"great":[78],"flexibility.":[79],"For":[80],"instance,":[81],"portable":[83],"multimedia":[84],"can":[86,110],"be":[87,111],"realized":[88],"by":[89],"only":[90],"three":[91],"chips:":[92],"an":[93,96],"chip,":[95,99],"I/O":[97],"ASIC":[98],"programming":[101],"ROM.":[102],"This":[103],"means":[104],"that":[105],"total":[107],"solution":[109],"achieved":[112],"at":[113],"lower":[115],"cost":[116],"higher":[118],"performance.":[119],"Personal":[120],"digital":[121,125],"assistants":[122],"(PDAs)":[123],"still":[126],"cameras":[127],"such":[129],"examples.":[130]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}