{"id":"https://openalex.org/W2109909594","doi":"https://doi.org/10.1109/icassp.1990.116004","title":"RNS approach to full parallel linear combinators","display_name":"RNS approach to full parallel linear combinators","publication_year":2002,"publication_date":"2002-12-04","ids":{"openalex":"https://openalex.org/W2109909594","doi":"https://doi.org/10.1109/icassp.1990.116004","mag":"2109909594"},"language":"en","primary_location":{"id":"doi:10.1109/icassp.1990.116004","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icassp.1990.116004","pdf_url":null,"source":{"id":"https://openalex.org/S4306419087","display_name":"International Conference on Acoustics, Speech, and Signal Processing","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Conference on Acoustics, Speech, and Signal Processing","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5048991707","display_name":"M\u00e1rio S\u00e9rgio Salerno","orcid":"https://orcid.org/0000-0002-2025-2534"},"institutions":[{"id":"https://openalex.org/I119003972","display_name":"Roma Tre University","ror":"https://ror.org/05vf0dg29","country_code":"IT","type":"education","lineage":["https://openalex.org/I119003972"]},{"id":"https://openalex.org/I116067653","display_name":"University of Rome Tor Vergata","ror":"https://ror.org/02p77k626","country_code":"IT","type":"education","lineage":["https://openalex.org/I116067653"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"M. Salerno","raw_affiliation_strings":["Department of Electronic Eng., University of Roma Tor Vergata, Rome, Italy","Dept. of Electron. Eng, Rome Univ., Italy"],"affiliations":[{"raw_affiliation_string":"Department of Electronic Eng., University of Roma Tor Vergata, Rome, Italy","institution_ids":["https://openalex.org/I116067653"]},{"raw_affiliation_string":"Dept. of Electron. Eng, Rome Univ., Italy","institution_ids":["https://openalex.org/I119003972"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5028297120","display_name":"G.C. Cardarilli","orcid":"https://orcid.org/0000-0002-7444-876X"},"institutions":[{"id":"https://openalex.org/I119003972","display_name":"Roma Tre University","ror":"https://ror.org/05vf0dg29","country_code":"IT","type":"education","lineage":["https://openalex.org/I119003972"]},{"id":"https://openalex.org/I116067653","display_name":"University of Rome Tor Vergata","ror":"https://ror.org/02p77k626","country_code":"IT","type":"education","lineage":["https://openalex.org/I116067653"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"G.C. Cardarilli","raw_affiliation_strings":["Department of Electronic Eng., University of Roma Tor Vergata, Rome, Italy","Dept. of Electron. Eng, Rome Univ., Italy"],"affiliations":[{"raw_affiliation_string":"Department of Electronic Eng., University of Roma Tor Vergata, Rome, Italy","institution_ids":["https://openalex.org/I116067653"]},{"raw_affiliation_string":"Dept. of Electron. Eng, Rome Univ., Italy","institution_ids":["https://openalex.org/I119003972"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5051950820","display_name":"R. Lojacono","orcid":null},"institutions":[{"id":"https://openalex.org/I116067653","display_name":"University of Rome Tor Vergata","ror":"https://ror.org/02p77k626","country_code":"IT","type":"education","lineage":["https://openalex.org/I116067653"]},{"id":"https://openalex.org/I119003972","display_name":"Roma Tre University","ror":"https://ror.org/05vf0dg29","country_code":"IT","type":"education","lineage":["https://openalex.org/I119003972"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"R. Lojacono","raw_affiliation_strings":["Department of Electronic Eng., University of Roma Tor Vergata, Rome, Italy","Dept. of Electron. Eng, Rome Univ., Italy"],"affiliations":[{"raw_affiliation_string":"Department of Electronic Eng., University of Roma Tor Vergata, Rome, Italy","institution_ids":["https://openalex.org/I116067653"]},{"raw_affiliation_string":"Dept. of Electron. Eng, Rome Univ., Italy","institution_ids":["https://openalex.org/I119003972"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5049258671","display_name":"F. Sargeni","orcid":"https://orcid.org/0000-0002-0131-236X"},"institutions":[{"id":"https://openalex.org/I116067653","display_name":"University of Rome Tor Vergata","ror":"https://ror.org/02p77k626","country_code":"IT","type":"education","lineage":["https://openalex.org/I116067653"]},{"id":"https://openalex.org/I119003972","display_name":"Roma Tre University","ror":"https://ror.org/05vf0dg29","country_code":"IT","type":"education","lineage":["https://openalex.org/I119003972"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"F. Sargeni","raw_affiliation_strings":["Department of Electronic Eng., University of Roma Tor Vergata, Rome, Italy","Dept. of Electron. Eng, Rome Univ., Italy"],"affiliations":[{"raw_affiliation_string":"Department of Electronic Eng., University of Roma Tor Vergata, Rome, Italy","institution_ids":["https://openalex.org/I116067653"]},{"raw_affiliation_string":"Dept. of Electron. Eng, Rome Univ., Italy","institution_ids":["https://openalex.org/I119003972"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5048991707"],"corresponding_institution_ids":["https://openalex.org/I116067653","https://openalex.org/I119003972"],"apc_list":null,"apc_paid":null,"fwci":0.9634,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.80769231,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"925","last_page":"928"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11693","display_name":"Cryptography and Residue Arithmetic","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1710","display_name":"Information Systems"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10951","display_name":"Cryptographic Implementations and Security","score":0.9944000244140625,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/combinatory-logic","display_name":"Combinatory logic","score":0.8339100480079651},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7246682643890381},{"id":"https://openalex.org/keywords/residue-number-system","display_name":"Residue number system","score":0.6055275201797485},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.5779665112495422},{"id":"https://openalex.org/keywords/modular-design","display_name":"Modular design","score":0.5764777064323425},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4554634988307953},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.448591411113739},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.39003151655197144},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.3224255442619324},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3112144470214844},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2376282811164856},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.22176402807235718},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.13750463724136353},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.1276058852672577}],"concepts":[{"id":"https://openalex.org/C79678938","wikidata":"https://www.wikidata.org/wiki/Q1481571","display_name":"Combinatory logic","level":2,"score":0.8339100480079651},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7246682643890381},{"id":"https://openalex.org/C71480937","wikidata":"https://www.wikidata.org/wiki/Q3086516","display_name":"Residue number system","level":2,"score":0.6055275201797485},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.5779665112495422},{"id":"https://openalex.org/C101468663","wikidata":"https://www.wikidata.org/wiki/Q1620158","display_name":"Modular design","level":2,"score":0.5764777064323425},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4554634988307953},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.448591411113739},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.39003151655197144},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.3224255442619324},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3112144470214844},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2376282811164856},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.22176402807235718},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.13750463724136353},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.1276058852672577},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icassp.1990.116004","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icassp.1990.116004","pdf_url":null,"source":{"id":"https://openalex.org/S4306419087","display_name":"International Conference on Acoustics, Speech, and Signal Processing","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Conference on Acoustics, Speech, and Signal Processing","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1561602969","https://openalex.org/W2070453147","https://openalex.org/W2080109292","https://openalex.org/W2124497708","https://openalex.org/W2149043711","https://openalex.org/W2153162789","https://openalex.org/W4239280186"],"related_works":["https://openalex.org/W2026765907","https://openalex.org/W4307413753","https://openalex.org/W1975604118","https://openalex.org/W119766800","https://openalex.org/W2313450777","https://openalex.org/W2162268423","https://openalex.org/W2988498873","https://openalex.org/W2771537172","https://openalex.org/W2140867083","https://openalex.org/W2184352159"],"abstract_inverted_index":{"Unconventional":[0],"number":[1,12,70],"systems":[2,13,26],"have":[3],"been":[4],"proposed":[5,54],"as":[6,63,79],"an":[7],"alternative":[8],"to":[9,29,103],"conventional":[10],"weighted":[11],"in":[14,36],"realizing":[15],"digital":[16],"signal":[17],"processing":[18],"(DSP)":[19],"processors.":[20],"A":[21],"well-known":[22,92],"advantage":[23,47],"of":[24,33,40,101,105,110],"these":[25],"is":[27,48,77],"related":[28],"the":[30,53,68,91,98],"intrinsic":[31],"property":[32],"performing":[34],"operations":[35],"a":[37,58,64],"finite":[38],"field":[39],"numbers,":[41],"thus":[42],"always":[43],"avoiding":[44],"overflow.":[45],"This":[46,95],"fully":[49],"met":[50],"by":[51,67,89],"applying":[52],"method,":[55],"which":[56,84],"realizes":[57],"full":[59],"parallel":[60,81],"linear":[61,75],"combinator":[62,76],"single":[65],"device":[66],"residue":[69],"system":[71],"(RNS)":[72],"approach.":[73],"The":[74],"implemented":[78],"two":[80],"modular":[82],"structures":[83],"can":[85],"work":[86],"very":[87],"quickly":[88],"means":[90],"isomorphism":[93],"technique.":[94],"technique":[96],"reduces":[97],"computational":[99],"costs":[100],"multipliers":[102],"that":[104],"adders.":[106],"Some":[107],"particular":[108],"aspects":[109],"VLSI":[111],"implementation":[112],"are":[113],"also":[114],"discussed.<":[115],"<ETX":[116],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[117],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">&gt;</ETX>":[118]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}