{"id":"https://openalex.org/W2147882650","doi":"https://doi.org/10.1109/icassp.1985.1168511","title":"Design strategies for implementing systolic and wavefront arrays using OCCAM","display_name":"Design strategies for implementing systolic and wavefront arrays using OCCAM","publication_year":2005,"publication_date":"2005-03-23","ids":{"openalex":"https://openalex.org/W2147882650","doi":"https://doi.org/10.1109/icassp.1985.1168511","mag":"2147882650"},"language":"en","primary_location":{"id":"doi:10.1109/icassp.1985.1168511","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icassp.1985.1168511","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ICASSP '85. IEEE International Conference on Acoustics, Speech, and Signal Processing","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5112003102","display_name":"R. Chapman","orcid":null},"institutions":[{"id":"https://openalex.org/I181647926","display_name":"University of Strathclyde","ror":"https://ror.org/00n3w3b69","country_code":"GB","type":"education","lineage":["https://openalex.org/I181647926"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"R. Chapman","raw_affiliation_strings":["University of Strathclyde, Glasgow, Scotland, UK"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Strathclyde, Glasgow, Scotland, UK","institution_ids":["https://openalex.org/I181647926"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5010254431","display_name":"T.S. Durrani","orcid":"https://orcid.org/0000-0002-8813-6118"},"institutions":[{"id":"https://openalex.org/I181647926","display_name":"University of Strathclyde","ror":"https://ror.org/00n3w3b69","country_code":"GB","type":"education","lineage":["https://openalex.org/I181647926"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"T. Durrani","raw_affiliation_strings":["Department of Electronic & Electrical Engineering, University of Strathclyde, Glasgow, UK"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronic & Electrical Engineering, University of Strathclyde, Glasgow, UK","institution_ids":["https://openalex.org/I181647926"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5002671420","display_name":"T. Joe Willey","orcid":null},"institutions":[{"id":"https://openalex.org/I4210156325","display_name":"Hewlett-Packard (United Kingdom)","ror":"https://ror.org/05g4mtv59","country_code":"GB","type":"company","lineage":["https://openalex.org/I1324840837","https://openalex.org/I4210156325"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"T. Willey","raw_affiliation_strings":["Research & Develognent Department, Hewlett Packard Limited, South Queensferry, UK"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Research & Develognent Department, Hewlett Packard Limited, South Queensferry, UK","institution_ids":["https://openalex.org/I4210156325"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.2739,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.68422004,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"10","issue":null,"first_page":"292","last_page":"295"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9848999977111816,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9848999977111816,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9764999747276306,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9717000126838684,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/occam","display_name":"occam","score":0.9892650246620178},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8319552540779114},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6374298334121704},{"id":"https://openalex.org/keywords/systolic-array","display_name":"Systolic array","score":0.6064007878303528},{"id":"https://openalex.org/keywords/code","display_name":"Code (set theory)","score":0.5367184281349182},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5220460891723633},{"id":"https://openalex.org/keywords/transputer","display_name":"Transputer","score":0.5175527930259705},{"id":"https://openalex.org/keywords/signal-processing","display_name":"Signal processing","score":0.44118061661720276},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.30360880494117737},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2292633056640625},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2149602174758911},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.1769583821296692},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.13251760601997375}],"concepts":[{"id":"https://openalex.org/C78469957","wikidata":"https://www.wikidata.org/wiki/Q838062","display_name":"occam","level":2,"score":0.9892650246620178},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8319552540779114},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6374298334121704},{"id":"https://openalex.org/C150741067","wikidata":"https://www.wikidata.org/wiki/Q2377218","display_name":"Systolic array","level":3,"score":0.6064007878303528},{"id":"https://openalex.org/C2776760102","wikidata":"https://www.wikidata.org/wiki/Q5139990","display_name":"Code (set theory)","level":3,"score":0.5367184281349182},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5220460891723633},{"id":"https://openalex.org/C2778319340","wikidata":"https://www.wikidata.org/wiki/Q776861","display_name":"Transputer","level":2,"score":0.5175527930259705},{"id":"https://openalex.org/C104267543","wikidata":"https://www.wikidata.org/wiki/Q208163","display_name":"Signal processing","level":3,"score":0.44118061661720276},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.30360880494117737},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2292633056640625},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2149602174758911},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.1769583821296692},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.13251760601997375},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icassp.1985.1168511","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icassp.1985.1168511","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ICASSP '85. IEEE International Conference on Acoustics, Speech, and Signal Processing","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W1581053260","https://openalex.org/W1581348750","https://openalex.org/W1964875728","https://openalex.org/W1997110943","https://openalex.org/W1998886707","https://openalex.org/W2060083504","https://openalex.org/W2138245082","https://openalex.org/W2148631003"],"related_works":["https://openalex.org/W2737943349","https://openalex.org/W646351947","https://openalex.org/W2741355684","https://openalex.org/W312586722","https://openalex.org/W2080808587","https://openalex.org/W1830328141","https://openalex.org/W2000750345","https://openalex.org/W2060083504","https://openalex.org/W4230360791","https://openalex.org/W2028628824"],"abstract_inverted_index":{"There":[0],"is":[1,65,76],"currently":[2],"significant":[3],"interest":[4],"in":[5,25],"the":[6,26,33,42,63,68,73,78,83],"use":[7],"of":[8,44,88],"highly":[9],"concurrent":[10],"processor":[11],"arrays":[12,57],"to":[13,21,40,71,81],"implement":[14],"signal":[15],"processing":[16],"algorithms":[17],"as":[18],"they":[19],"lead":[20],"a":[22],"substantial":[23],"reduction":[24],"computational":[27,74],"time.":[28],"This":[29,47],"paper":[30],"shows":[31],"how":[32],"OCCAM":[34,66],"programming":[35],"language":[36],"can":[37,58],"be":[38,59],"used":[39,70],"aid":[41],"design":[43,48],"such":[45],"architectures.":[46],"approach":[49],"has":[50],"several":[51],"interesting":[52],"features:":[53],"systolic":[54],"and":[55,61],"wavefront":[56],"designed,":[60],"since":[62],"method":[64],"based,":[67],"algebra":[69],"describe":[72],"structure":[75],"also":[77],"code":[79],"required":[80],"program":[82],"algorithm":[84],"on":[85],"an":[86],"array":[87],"INMOS":[89],"IMS":[90],"T424":[91],"transputers,":[92],"INTEL":[93],"8086":[94],"processors,":[95],"or":[96],"Motorola":[97],"68000":[98],"processors.":[99]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}