{"id":"https://openalex.org/W1522038563","doi":"https://doi.org/10.1109/icassp.1985.1168510","title":"Hierarchical flowgraph integration for VLSI array processors","display_name":"Hierarchical flowgraph integration for VLSI array processors","publication_year":2005,"publication_date":"2005-03-23","ids":{"openalex":"https://openalex.org/W1522038563","doi":"https://doi.org/10.1109/icassp.1985.1168510","mag":"1522038563"},"language":"en","primary_location":{"id":"doi:10.1109/icassp.1985.1168510","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icassp.1985.1168510","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ICASSP '85. IEEE International Conference on Acoustics, Speech, and Signal Processing","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5072714962","display_name":"Sun\u2010Yuan Kung","orcid":"https://orcid.org/0000-0002-7314-0720"},"institutions":[{"id":"https://openalex.org/I1174212","display_name":"University of Southern California","ror":"https://ror.org/03taz7m60","country_code":"US","type":"education","lineage":["https://openalex.org/I1174212"]},{"id":"https://openalex.org/I2800817003","display_name":"California Southern University","ror":"https://ror.org/058zz0t50","country_code":"US","type":"education","lineage":["https://openalex.org/I2800817003"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"S. Kung","raw_affiliation_strings":["Department of Electrical Engineering, University of Southern California, USA","University of Southern California"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, University of Southern California, USA","institution_ids":["https://openalex.org/I1174212"]},{"raw_affiliation_string":"University of Southern California","institution_ids":["https://openalex.org/I2800817003","https://openalex.org/I1174212"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5043710783","display_name":"J. Annevelink","orcid":null},"institutions":[{"id":"https://openalex.org/I1174212","display_name":"University of Southern California","ror":"https://ror.org/03taz7m60","country_code":"US","type":"education","lineage":["https://openalex.org/I1174212"]},{"id":"https://openalex.org/I2800817003","display_name":"California Southern University","ror":"https://ror.org/058zz0t50","country_code":"US","type":"education","lineage":["https://openalex.org/I2800817003"]},{"id":"https://openalex.org/I98358874","display_name":"Delft University of Technology","ror":"https://ror.org/02e2c7k09","country_code":"NL","type":"education","lineage":["https://openalex.org/I98358874"]}],"countries":["NL","US"],"is_corresponding":false,"raw_author_name":"J. Annevelink","raw_affiliation_strings":["Department of Electrical Engineering, Delft University of Technnology, Netherlands","University of Southern California"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Delft University of Technnology, Netherlands","institution_ids":["https://openalex.org/I98358874"]},{"raw_affiliation_string":"University of Southern California","institution_ids":["https://openalex.org/I2800817003","https://openalex.org/I1174212"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5035921496","display_name":"P. Dewilde","orcid":"https://orcid.org/0000-0002-9553-1845"},"institutions":[{"id":"https://openalex.org/I1174212","display_name":"University of Southern California","ror":"https://ror.org/03taz7m60","country_code":"US","type":"education","lineage":["https://openalex.org/I1174212"]},{"id":"https://openalex.org/I2800817003","display_name":"California Southern University","ror":"https://ror.org/058zz0t50","country_code":"US","type":"education","lineage":["https://openalex.org/I2800817003"]},{"id":"https://openalex.org/I98358874","display_name":"Delft University of Technology","ror":"https://ror.org/02e2c7k09","country_code":"NL","type":"education","lineage":["https://openalex.org/I98358874"]}],"countries":["NL","US"],"is_corresponding":false,"raw_author_name":"P. Dewilde","raw_affiliation_strings":["Department of Electrical Engineering, Delft University of Technnology, Netherlands","University of Southern California"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Delft University of Technnology, Netherlands","institution_ids":["https://openalex.org/I98358874"]},{"raw_affiliation_string":"University of Southern California","institution_ids":["https://openalex.org/I2800817003","https://openalex.org/I1174212"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5059943567","display_name":"S. C. Lo","orcid":null},"institutions":[{"id":"https://openalex.org/I1174212","display_name":"University of Southern California","ror":"https://ror.org/03taz7m60","country_code":"US","type":"education","lineage":["https://openalex.org/I1174212"]},{"id":"https://openalex.org/I2800817003","display_name":"California Southern University","ror":"https://ror.org/058zz0t50","country_code":"US","type":"education","lineage":["https://openalex.org/I2800817003"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"S. Lo","raw_affiliation_strings":["Department of Electrical Engineering, University of Southern California, USA","University of Southern California"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, University of Southern California, USA","institution_ids":["https://openalex.org/I1174212"]},{"raw_affiliation_string":"University of Southern California","institution_ids":["https://openalex.org/I2800817003","https://openalex.org/I1174212"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.06016277,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"10","issue":null,"first_page":"288","last_page":"291"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9973000288009644,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9962000250816345,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.8595670461654663},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7776120901107788},{"id":"https://openalex.org/keywords/signal-flow-graph","display_name":"Signal-flow graph","score":0.6336471438407898},{"id":"https://openalex.org/keywords/data-flow-diagram","display_name":"Data flow diagram","score":0.5673238635063171},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5008664131164551},{"id":"https://openalex.org/keywords/decomposition","display_name":"Decomposition","score":0.4987335205078125},{"id":"https://openalex.org/keywords/signal-processing","display_name":"Signal processing","score":0.47227346897125244},{"id":"https://openalex.org/keywords/graph","display_name":"Graph","score":0.45862478017807007},{"id":"https://openalex.org/keywords/notation","display_name":"Notation","score":0.4497973620891571},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.44204485416412354},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4418778419494629},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.3885011374950409},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3699721693992615},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3224692940711975},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.19083371758460999},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.16627666354179382},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.1584368646144867}],"concepts":[{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.8595670461654663},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7776120901107788},{"id":"https://openalex.org/C166501922","wikidata":"https://www.wikidata.org/wiki/Q1786523","display_name":"Signal-flow graph","level":2,"score":0.6336471438407898},{"id":"https://openalex.org/C489000","wikidata":"https://www.wikidata.org/wiki/Q747385","display_name":"Data flow diagram","level":2,"score":0.5673238635063171},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5008664131164551},{"id":"https://openalex.org/C124681953","wikidata":"https://www.wikidata.org/wiki/Q339062","display_name":"Decomposition","level":2,"score":0.4987335205078125},{"id":"https://openalex.org/C104267543","wikidata":"https://www.wikidata.org/wiki/Q208163","display_name":"Signal processing","level":3,"score":0.47227346897125244},{"id":"https://openalex.org/C132525143","wikidata":"https://www.wikidata.org/wiki/Q141488","display_name":"Graph","level":2,"score":0.45862478017807007},{"id":"https://openalex.org/C45357846","wikidata":"https://www.wikidata.org/wiki/Q2001982","display_name":"Notation","level":2,"score":0.4497973620891571},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.44204485416412354},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4418778419494629},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.3885011374950409},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3699721693992615},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3224692940711975},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.19083371758460999},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.16627666354179382},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.1584368646144867},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0},{"id":"https://openalex.org/C18903297","wikidata":"https://www.wikidata.org/wiki/Q7150","display_name":"Ecology","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icassp.1985.1168510","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icassp.1985.1168510","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ICASSP '85. IEEE International Conference on Acoustics, Speech, and Signal Processing","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W1509443229","https://openalex.org/W1809252806","https://openalex.org/W2071696716","https://openalex.org/W2138245082","https://openalex.org/W6630562399","https://openalex.org/W6680419662"],"related_works":["https://openalex.org/W2673800974","https://openalex.org/W4389544198","https://openalex.org/W157109213","https://openalex.org/W2052543411","https://openalex.org/W1998390211","https://openalex.org/W2129211971","https://openalex.org/W2062771600","https://openalex.org/W2117305543","https://openalex.org/W2035871485","https://openalex.org/W1655426301"],"abstract_inverted_index":{"The":[0,24,81,101],"structural":[1,120],"properties":[2],"of":[3,11,37,78],"parallel":[4],"recursive":[5,107],"algorithms":[6],"point":[7],"to":[8,30,60,68,74,138],"the":[9,28,34,106],"feasibility":[10],"a":[12,45,87],"Hierarchical":[13,25],"Flow-graph":[14],"integration":[15,63,77],"(HIFI)":[16],"design":[17,88],"method":[18,83],"for":[19,50,97],"VLSI":[20,69,95],"array":[21,70,137],"processor":[22],"design.":[23],"approach":[26],"allows":[27],"designer":[29],"focus":[31],"attention":[32],"at":[33,94],"appropriate":[35],"level":[36],"detail.":[38],"Flow-graphs":[39],"are":[40],"used":[41,58],"because":[42],"they":[43],"offer":[44],"powerful":[46],"and":[47,89,114,119,126,130,133],"convenient":[48],"tool":[49,91],"describing":[51],"many":[52],"signal":[53,98],"processing":[54,99],"algorithms.":[55,100],"Integration":[56],"is":[57,84],"here":[59],"mean":[61],"top-down":[62],"-":[64,71],"from":[65,135],"algorithm":[66,108],"analysis":[67],"as":[72,86],"opposed":[73],"merely":[75],"an":[76],"electronic":[79],"components.":[80],"HIFI":[82],"proposed":[85],"description":[90],"aiming":[92],"specially":[93],"arrays":[96],"major":[102],"issues":[103],"involved":[104],"are:":[105],"decomposition,":[109,121],"abstract":[110],"notations,":[111],"flow-graph":[112],"(structural)":[113],"functional":[115],"(behavior)":[116],"description,":[117],"temporal":[118],"bi-directional":[122],"mapping":[123,134],"between":[124],"graphic":[125],"textual":[127],"codes,":[128],"simulation":[129],"verification":[131],"tools,":[132],"virtual":[136],"actual":[139],"architecture.":[140]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}