{"id":"https://openalex.org/W2120754438","doi":"https://doi.org/10.1109/icassp.1985.1168472","title":"The application of multi-dimensional access memories to ultra high performance signal processing systems","display_name":"The application of multi-dimensional access memories to ultra high performance signal processing systems","publication_year":2005,"publication_date":"2005-03-23","ids":{"openalex":"https://openalex.org/W2120754438","doi":"https://doi.org/10.1109/icassp.1985.1168472","mag":"2120754438"},"language":"en","primary_location":{"id":"doi:10.1109/icassp.1985.1168472","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icassp.1985.1168472","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ICASSP '85. IEEE International Conference on Acoustics, Speech, and Signal Processing","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5081882998","display_name":"David L. Hayes","orcid":"https://orcid.org/0000-0002-0326-1180"},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"D. Hayes","raw_affiliation_strings":["Signal Processing Design Department The Research Laboratory, GEC Avionics Limited, Hertfordshire, UK"],"affiliations":[{"raw_affiliation_string":"Signal Processing Design Department The Research Laboratory, GEC Avionics Limited, Hertfordshire, UK","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5070964039","display_name":"Bill Strawhorne","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"B. Strawhorne","raw_affiliation_strings":["Signal Processing Design Department The Research Laboratory, GEC Avionics Limited, Hertfordshire, UK"],"affiliations":[{"raw_affiliation_string":"Signal Processing Design Department The Research Laboratory, GEC Avionics Limited, Hertfordshire, UK","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5081882998"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.18516156,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"10","issue":null,"first_page":"1412","last_page":"1415"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9976999759674072,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8303077220916748},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.5948114395141602},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.5945291519165039},{"id":"https://openalex.org/keywords/signal-processing","display_name":"Signal processing","score":0.4940226674079895},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.48408496379852295},{"id":"https://openalex.org/keywords/concurrency","display_name":"Concurrency","score":0.48037606477737427},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.4418973922729492},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3496604561805725},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.32853618264198303},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2677227258682251},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.14172479510307312},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.13570216298103333}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8303077220916748},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.5948114395141602},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.5945291519165039},{"id":"https://openalex.org/C104267543","wikidata":"https://www.wikidata.org/wiki/Q208163","display_name":"Signal processing","level":3,"score":0.4940226674079895},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.48408496379852295},{"id":"https://openalex.org/C193702766","wikidata":"https://www.wikidata.org/wiki/Q1414548","display_name":"Concurrency","level":2,"score":0.48037606477737427},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.4418973922729492},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3496604561805725},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.32853618264198303},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2677227258682251},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.14172479510307312},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.13570216298103333},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icassp.1985.1168472","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icassp.1985.1168472","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ICASSP '85. IEEE International Conference on Acoustics, Speech, and Signal Processing","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":1,"referenced_works":["https://openalex.org/W2153691819"],"related_works":["https://openalex.org/W2081032080","https://openalex.org/W2134733504","https://openalex.org/W2144460576","https://openalex.org/W2374241634","https://openalex.org/W1617740971","https://openalex.org/W2134640991","https://openalex.org/W3027318491","https://openalex.org/W1607753725","https://openalex.org/W1979789826","https://openalex.org/W1986774039"],"abstract_inverted_index":{"A":[0],"multi-dimensional":[1],"access":[2],"memory":[3],"(MDAM)":[4],"allows":[5],"a":[6,24,40],"word":[7],"to":[8,50,77,108],"be":[9,51,91],"accessed":[10],"from":[11],"store":[12],"either":[13],"in":[14,80],"the":[15,36,45],"manner":[16],"it":[17,105],"was":[18],"entered":[19],"or":[20,29],"as":[21],"part":[22],"of":[23,27,35,39,68,87,119],"bit":[25,55],"slice":[26],"centigucus":[28],"equally":[30],"spaced":[31],"words.":[32],"The":[33],"mapping":[34],"natural":[37],"multi-dimensionality":[38],"signal":[41],"processing":[42],"task":[43],"onto":[44],"MDAM":[46],"structure":[47],"is":[48,106],"shown":[49],"particularly":[52],"useful":[53],"when":[54],"serial/bit":[56],"parallel":[57,111],"(BS/BP)":[58],"processers":[59],"are":[60,71,74],"employed.":[61],"Highly":[62],"efficient":[63],"and":[64,97],"deeply":[65],"pipelined":[66],"implementations":[67],"MDAM/processer":[69],"structures":[70,113],"discussed":[72],"that":[73,81,114],"well":[75],"suited":[76],"VLSI":[78],"methodologies,":[79],"very":[82,116],"wide":[83],"bandwidth":[84],"interconnection":[85],"networks":[86],"high":[88,117],"complexity":[89],"can":[90],"achieved":[92],"at":[93],"relatively":[94],"low":[95],"gate":[96],"pin":[98],"counts":[99],"(at":[100],"both":[101],"super/sub-micron":[102],"levels).":[103],"Thus":[104],"possible":[107],"form":[109],"highly":[110],"multi-MDAM/processer":[112],"support":[115],"levels":[118],"concurrency.":[120]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}