{"id":"https://openalex.org/W1486317039","doi":"https://doi.org/10.1109/icassp.1984.1172761","title":"A bit serial linear array DFT","display_name":"A bit serial linear array DFT","publication_year":2005,"publication_date":"2005-03-24","ids":{"openalex":"https://openalex.org/W1486317039","doi":"https://doi.org/10.1109/icassp.1984.1172761","mag":"1486317039"},"language":"en","primary_location":{"id":"doi:10.1109/icassp.1984.1172761","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icassp.1984.1172761","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ICASSP '84. IEEE International Conference on Acoustics, Speech, and Signal Processing","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5030835825","display_name":"G.H. Allen","orcid":null},"institutions":[{"id":"https://openalex.org/I86467917","display_name":"James Cook University","ror":"https://ror.org/04gsp2c11","country_code":"AU","type":"education","lineage":["https://openalex.org/I86467917"]}],"countries":["AU"],"is_corresponding":true,"raw_author_name":"G. Allen","raw_affiliation_strings":["Department of Electrical and Electronic Engineering, James Cook University, Australia"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Electronic Engineering, James Cook University, Australia","institution_ids":["https://openalex.org/I86467917"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5080915733","display_name":"P.B. Denyer","orcid":null},"institutions":[{"id":"https://openalex.org/I98677209","display_name":"University of Edinburgh","ror":"https://ror.org/01nrxwf90","country_code":"GB","type":"education","lineage":["https://openalex.org/I98677209"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"P. Denyer","raw_affiliation_strings":["Department of Electrical Engineering, University of Edinburgh, Edinburgh, UK"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, University of Edinburgh, Edinburgh, UK","institution_ids":["https://openalex.org/I98677209"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5108527490","display_name":"D. Renshaw","orcid":null},"institutions":[{"id":"https://openalex.org/I98677209","display_name":"University of Edinburgh","ror":"https://ror.org/01nrxwf90","country_code":"GB","type":"education","lineage":["https://openalex.org/I98677209"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"D. Renshaw","raw_affiliation_strings":["Department of Electrical Engineering, University of Edinburgh, Edinburgh, UK"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, University of Edinburgh, Edinburgh, UK","institution_ids":["https://openalex.org/I98677209"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5030835825"],"corresponding_institution_ids":["https://openalex.org/I86467917"],"apc_list":null,"apc_paid":null,"fwci":0.6358,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.65387888,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"9","issue":null,"first_page":"230","last_page":"233"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9961000084877014,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9933000206947327,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6422407627105713},{"id":"https://openalex.org/keywords/nmos-logic","display_name":"NMOS logic","score":0.620326042175293},{"id":"https://openalex.org/keywords/polynomial","display_name":"Polynomial","score":0.5935174822807312},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.5453842878341675},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.5048030614852905},{"id":"https://openalex.org/keywords/sequence","display_name":"Sequence (biology)","score":0.4452553391456604},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.43713000416755676},{"id":"https://openalex.org/keywords/signal-processing","display_name":"Signal processing","score":0.4289880394935608},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4259006679058075},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.415849506855011},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3779470920562744},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.22885239124298096},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.2138265073299408},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.1387927234172821},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.11083078384399414},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.09184199571609497},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.09021508693695068}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6422407627105713},{"id":"https://openalex.org/C197162436","wikidata":"https://www.wikidata.org/wiki/Q83908","display_name":"NMOS logic","level":4,"score":0.620326042175293},{"id":"https://openalex.org/C90119067","wikidata":"https://www.wikidata.org/wiki/Q43260","display_name":"Polynomial","level":2,"score":0.5935174822807312},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.5453842878341675},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.5048030614852905},{"id":"https://openalex.org/C2778112365","wikidata":"https://www.wikidata.org/wiki/Q3511065","display_name":"Sequence (biology)","level":2,"score":0.4452553391456604},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.43713000416755676},{"id":"https://openalex.org/C104267543","wikidata":"https://www.wikidata.org/wiki/Q208163","display_name":"Signal processing","level":3,"score":0.4289880394935608},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4259006679058075},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.415849506855011},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3779470920562744},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.22885239124298096},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.2138265073299408},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.1387927234172821},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.11083078384399414},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.09184199571609497},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.09021508693695068},{"id":"https://openalex.org/C54355233","wikidata":"https://www.wikidata.org/wiki/Q7162","display_name":"Genetics","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icassp.1984.1172761","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icassp.1984.1172761","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ICASSP '84. IEEE International Conference on Acoustics, Speech, and Signal Processing","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W1496796147","https://openalex.org/W1593183029","https://openalex.org/W2001076178","https://openalex.org/W2073335165","https://openalex.org/W3144025793","https://openalex.org/W6635425850"],"related_works":["https://openalex.org/W2217098757","https://openalex.org/W2796085262","https://openalex.org/W2263373136","https://openalex.org/W190245591","https://openalex.org/W1650778624","https://openalex.org/W2545385022","https://openalex.org/W2022549222","https://openalex.org/W2082944690","https://openalex.org/W1486119332","https://openalex.org/W2187980602"],"abstract_inverted_index":{"A":[0,141],"Linear":[1],"array":[2,21,74,94],"which":[3,117],"computes":[4],"the":[5,18,38,46,53,56,61,73,76,82,93,110,130,156,161],"DFT":[6,39,77],"in":[7,89,92],"a":[8,41,96,103,113],"pipelined":[9],"fashion":[10],"is":[11,15,40,79,99,118],"described.":[12],"The":[13,84],"algorithm":[14],"derived":[16],"from":[17,81],"batch":[19,98],"processing":[20],"proposed":[22],"by":[23],"H.T.":[24],"Kung":[25],"[1]":[26],"but":[27],"has":[28,112,150],"been":[29,151],"modified":[30],"to":[31],"allow":[32],"continuous":[33],"operation.":[34],"This":[35],"computation":[36],"of":[37,65,72,163],"complex":[42,63],"polynomial":[43,57,85],"evaluation":[44],"on":[45],"unit":[47],"circle":[48],"using":[49,155],"Horner's":[50],"method":[51],"having":[52],"data":[54],"for":[55,122,138,145],"coefficients.":[58],"Data":[59],"and":[60,75,95,133,153],"N-th":[62],"roots":[64],"unity":[66],"are":[67,87],"input":[68],"at":[69,160],"one":[70],"end":[71],"sequence":[78],"output":[80],"other.":[83],"coefficients":[86],"stored":[88],"successive":[90],"modules":[91,129],"new":[97],"latched":[100],"successively":[101],"with":[102],"synchronising":[104],"signal.":[105],"In":[106],"its":[107],"simplest":[108],"form":[109],"design":[111],"single":[114],"system":[115,131],"part":[116],"replicated":[119],"N":[120],"times":[121],"an":[123],"N-point":[124],"transform.":[125],"For":[126],"time":[127],"multiplexed":[128],"throughput":[132],"hardware":[134],"can":[135],"be":[136],"optimised":[137],"given":[139],"applications.":[140],"bit":[142],"serial":[143],"layout":[144],"6":[146],"micron":[147],"NMOS":[148],"VLSI":[149],"designed":[152],"simulated":[154],"FIRST":[157],"silicon":[158],"compiler":[159],"University":[162],"Edinburgh.":[164]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
