{"id":"https://openalex.org/W2158210004","doi":"https://doi.org/10.1109/icassp.1982.1171585","title":"A VLSI I/O chip for multiple signal processor architectures","display_name":"A VLSI I/O chip for multiple signal processor architectures","publication_year":2005,"publication_date":"2005-03-24","ids":{"openalex":"https://openalex.org/W2158210004","doi":"https://doi.org/10.1109/icassp.1982.1171585","mag":"2158210004"},"language":"en","primary_location":{"id":"doi:10.1109/icassp.1982.1171585","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icassp.1982.1171585","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ICASSP '82. IEEE International Conference on Acoustics, Speech, and Signal Processing","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5059071601","display_name":"Alexander Frey","orcid":null},"institutions":[{"id":"https://openalex.org/I1341412227","display_name":"IBM (United States)","ror":"https://ror.org/05hh8d621","country_code":"US","type":"company","lineage":["https://openalex.org/I1341412227"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"A. Frey","raw_affiliation_strings":["Federal Systems Division, International Business Machines Corporation, Manassas, VA, USA"],"affiliations":[{"raw_affiliation_string":"Federal Systems Division, International Business Machines Corporation, Manassas, VA, USA","institution_ids":["https://openalex.org/I1341412227"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5059071601"],"corresponding_institution_ids":["https://openalex.org/I1341412227"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.22672194,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"7","issue":null,"first_page":"1057","last_page":"1060"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9926000237464905,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9926000237464905,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9828000068664551,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.975600004196167,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7286566495895386},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.6679022312164307},{"id":"https://openalex.org/keywords/signal-flow-graph","display_name":"Signal-flow graph","score":0.6084913611412048},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5831103920936584},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.5304474234580994},{"id":"https://openalex.org/keywords/data-flow-diagram","display_name":"Data flow diagram","score":0.5143119096755981},{"id":"https://openalex.org/keywords/network-on-a-chip","display_name":"Network on a chip","score":0.4754697382450104},{"id":"https://openalex.org/keywords/signal-processing","display_name":"Signal processing","score":0.47517696022987366},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.41403859853744507},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4015718400478363},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3999560475349426},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.24778419733047485},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.15716689825057983},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.14439070224761963},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.09720483422279358}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7286566495895386},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.6679022312164307},{"id":"https://openalex.org/C166501922","wikidata":"https://www.wikidata.org/wiki/Q1786523","display_name":"Signal-flow graph","level":2,"score":0.6084913611412048},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5831103920936584},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.5304474234580994},{"id":"https://openalex.org/C489000","wikidata":"https://www.wikidata.org/wiki/Q747385","display_name":"Data flow diagram","level":2,"score":0.5143119096755981},{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.4754697382450104},{"id":"https://openalex.org/C104267543","wikidata":"https://www.wikidata.org/wiki/Q208163","display_name":"Signal processing","level":3,"score":0.47517696022987366},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.41403859853744507},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4015718400478363},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3999560475349426},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.24778419733047485},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.15716689825057983},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.14439070224761963},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.09720483422279358},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icassp.1982.1171585","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icassp.1982.1171585","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ICASSP '82. IEEE International Conference on Acoustics, Speech, and Signal Processing","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.6700000166893005}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":2,"referenced_works":["https://openalex.org/W2151762706","https://openalex.org/W6682368828"],"related_works":["https://openalex.org/W2673800974","https://openalex.org/W4389544198","https://openalex.org/W157109213","https://openalex.org/W2052543411","https://openalex.org/W1998390211","https://openalex.org/W2129211971","https://openalex.org/W2062771600","https://openalex.org/W2279426828","https://openalex.org/W2117305543","https://openalex.org/W2035871485"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"the":[3,45],"design":[4],"features":[5],"of":[6,18,40],"a":[7,16,23,29,34],"Signal":[8],"Processing":[9],"Input/Output":[10],"(SPIO)":[11],"chip":[12],"intended":[13],"for":[14],"interconnecting":[15],"multiplicity":[17],"micro":[19],"signal":[20],"processors":[21,46],"within":[22],"cabinet.":[24],"Interfaces":[25],"to":[26,50],"support":[27],"both":[28],"data":[30,54],"transfer":[31],"network":[32,36],"and":[33],"control":[35],"are":[37,56],"described.":[38],"Examples":[39],"several":[41],"configurations":[42],"in":[43],"which":[44],"could":[47],"be":[48],"interconnected":[49],"follow":[51],"an":[52],"application":[53],"flow":[55],"given.":[57]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}