{"id":"https://openalex.org/W1912488282","doi":"https://doi.org/10.1109/icassp.1982.1171584","title":"An integrated processor for adaptive and parallel algorithms","display_name":"An integrated processor for adaptive and parallel algorithms","publication_year":2005,"publication_date":"2005-03-24","ids":{"openalex":"https://openalex.org/W1912488282","doi":"https://doi.org/10.1109/icassp.1982.1171584","mag":"1912488282"},"language":"en","primary_location":{"id":"doi:10.1109/icassp.1982.1171584","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icassp.1982.1171584","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ICASSP '82. IEEE International Conference on Acoustics, Speech, and Signal Processing","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5005467230","display_name":"M. Cand","orcid":null},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"M. Cand","raw_affiliation_strings":["Centre National d''Etudes Des Telecommunications, Grenoble, France"],"affiliations":[{"raw_affiliation_string":"Centre National d''Etudes Des Telecommunications, Grenoble, France","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5012659355","display_name":"Patrice Le Scan","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"P. Le Scan","raw_affiliation_strings":["Centre National d''Etudes Des Telecommunications, Grenoble, France"],"affiliations":[{"raw_affiliation_string":"Centre National d''Etudes Des Telecommunications, Grenoble, France","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5045289659","display_name":"Alain Roset","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"A. Roset","raw_affiliation_strings":["Centre National d''Etudes Des Telecommunications, Grenoble, France"],"affiliations":[{"raw_affiliation_string":"Centre National d''Etudes Des Telecommunications, Grenoble, France","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5005467230"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.09959609,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"7","issue":null,"first_page":"1069","last_page":"1072"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9957000017166138,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9957000017166138,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9818999767303467,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9663000106811523,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8124567270278931},{"id":"https://openalex.org/keywords/digital-signal-processor","display_name":"Digital signal processor","score":0.5650875568389893},{"id":"https://openalex.org/keywords/16-bit","display_name":"16-bit","score":0.559953510761261},{"id":"https://openalex.org/keywords/32-bit","display_name":"32-bit","score":0.5468938946723938},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.5436850786209106},{"id":"https://openalex.org/keywords/nmos-logic","display_name":"NMOS logic","score":0.5353332757949829},{"id":"https://openalex.org/keywords/accumulator","display_name":"Accumulator (cryptography)","score":0.5224503874778748},{"id":"https://openalex.org/keywords/multiplier","display_name":"Multiplier (economics)","score":0.5104147791862488},{"id":"https://openalex.org/keywords/control-unit","display_name":"Control unit","score":0.4444335997104645},{"id":"https://openalex.org/keywords/arithmetic-logic-unit","display_name":"Arithmetic logic unit","score":0.4326157569885254},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.42892494797706604},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4123704731464386},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.3720681667327881},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3628109097480774},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3346089720726013},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.2698303759098053},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.12031823396682739}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8124567270278931},{"id":"https://openalex.org/C161611012","wikidata":"https://www.wikidata.org/wiki/Q106370","display_name":"Digital signal processor","level":3,"score":0.5650875568389893},{"id":"https://openalex.org/C33652231","wikidata":"https://www.wikidata.org/wiki/Q194368","display_name":"16-bit","level":2,"score":0.559953510761261},{"id":"https://openalex.org/C75695347","wikidata":"https://www.wikidata.org/wiki/Q225147","display_name":"32-bit","level":2,"score":0.5468938946723938},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.5436850786209106},{"id":"https://openalex.org/C197162436","wikidata":"https://www.wikidata.org/wiki/Q83908","display_name":"NMOS logic","level":4,"score":0.5353332757949829},{"id":"https://openalex.org/C2078106","wikidata":"https://www.wikidata.org/wiki/Q14906620","display_name":"Accumulator (cryptography)","level":2,"score":0.5224503874778748},{"id":"https://openalex.org/C124584101","wikidata":"https://www.wikidata.org/wiki/Q1053266","display_name":"Multiplier (economics)","level":2,"score":0.5104147791862488},{"id":"https://openalex.org/C81988521","wikidata":"https://www.wikidata.org/wiki/Q676838","display_name":"Control unit","level":2,"score":0.4444335997104645},{"id":"https://openalex.org/C100276221","wikidata":"https://www.wikidata.org/wiki/Q192903","display_name":"Arithmetic logic unit","level":2,"score":0.4326157569885254},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.42892494797706604},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4123704731464386},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.3720681667327881},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3628109097480774},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3346089720726013},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2698303759098053},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.12031823396682739},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icassp.1982.1171584","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icassp.1982.1171584","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ICASSP '82. IEEE International Conference on Acoustics, Speech, and Signal Processing","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.6499999761581421}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W1670746658","https://openalex.org/W1897055341","https://openalex.org/W2026211490","https://openalex.org/W2045721859","https://openalex.org/W2070773415"],"related_works":["https://openalex.org/W2582964071","https://openalex.org/W2382902254","https://openalex.org/W2129001793","https://openalex.org/W2791606710","https://openalex.org/W4232288504","https://openalex.org/W1516141068","https://openalex.org/W2900572407","https://openalex.org/W1572471198","https://openalex.org/W2147143221","https://openalex.org/W3020807053"],"abstract_inverted_index":{"The":[0],"architecture":[1],"and":[2,27,30,98,102,107,119],"some":[3,28],"basic":[4],"applications":[5],"of":[6,36,61,67,76,93,110],"a":[7,81,86,99],"single-chip":[8],"software-programmable":[9],"digital":[10],"signal":[11],"processor":[12],"are":[13,45,112],"presented.":[14],"This":[15,78],"NMOS":[16],"3.5":[17],"um":[18],"silicon":[19],"gate":[20],"circuit":[21,79],"is":[22,59],"well-suited":[23],"for":[24],"adaptive":[25],"algorithms":[26],"input":[29],"output":[31],"features":[32],"allow":[33],"easy":[34],"implementation":[35],"multiprocessing":[37],"architectures":[38],"using":[39,131],"several":[40],"chips.":[41],"These":[42],"I/O":[43],"ports":[44],"designed":[46],"to":[47,89],"transfer":[48,66],"data":[49,116],"serially":[50],"or":[51,65,124],"through":[52],"an":[53,62,70],"8-bit":[54],"bus.":[55],"Their":[56],"main":[57],"feature":[58],"control":[60],"internal":[63],"program":[64],"instructions":[68],"from":[69],"external":[71],"memory":[72],"without":[73],"any":[74],"loss":[75],"speed.":[77],"incorporates":[80],"16\u00d716":[82],"bit":[83,96,126],"hardware":[84],"multiplier,":[85],"powerful":[87],"unit":[88,104],"compute":[90],"the":[91],"addresses":[92],"two":[94,115],"128\u00d716":[95],"RAMs":[97],"32-bit":[100],"arithmetic":[101],"logical":[103],"with":[105],"accumulator":[106],"stack,":[108],"all":[109],"which":[111],"connected":[113],"by":[114],"buses":[117],"(16":[118],"25b":[120],"wide).":[121],"Either":[122],"16-":[123],"25-":[125],"words":[127],"can":[128],"be":[129],"processed":[130],"this":[132],"circuit.":[133]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
