{"id":"https://openalex.org/W2125608394","doi":"https://doi.org/10.1109/icassp.1981.1171244","title":"An LSI chip set for DSP hardware implementation","display_name":"An LSI chip set for DSP hardware implementation","publication_year":2005,"publication_date":"2005-03-24","ids":{"openalex":"https://openalex.org/W2125608394","doi":"https://doi.org/10.1109/icassp.1981.1171244","mag":"2125608394"},"language":"en","primary_location":{"id":"doi:10.1109/icassp.1981.1171244","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icassp.1981.1171244","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ICASSP '81. IEEE International Conference on Acoustics, Speech, and Signal Processing","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://kanazawa-u.repo.nii.ac.jp/records/7910","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5079191387","display_name":"A. Kanemasa","orcid":null},"institutions":[{"id":"https://openalex.org/I118347220","display_name":"NEC (Japan)","ror":"https://ror.org/04jndar25","country_code":"JP","type":"company","lineage":["https://openalex.org/I118347220"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"A. Kanemasa","raw_affiliation_strings":["Nippon Electric Company Limited, Kawasaki, Miyazaki, Japan"],"affiliations":[{"raw_affiliation_string":"Nippon Electric Company Limited, Kawasaki, Miyazaki, Japan","institution_ids":["https://openalex.org/I118347220"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5108502616","display_name":"R. Maruta","orcid":null},"institutions":[{"id":"https://openalex.org/I118347220","display_name":"NEC (Japan)","ror":"https://ror.org/04jndar25","country_code":"JP","type":"company","lineage":["https://openalex.org/I118347220"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"R. Maruta","raw_affiliation_strings":["Nippon Electric Company Limited, Kawasaki, Miyazaki, Japan"],"affiliations":[{"raw_affiliation_string":"Nippon Electric Company Limited, Kawasaki, Miyazaki, Japan","institution_ids":["https://openalex.org/I118347220"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5109343305","display_name":"Kenji Nakayama","orcid":null},"institutions":[{"id":"https://openalex.org/I118347220","display_name":"NEC (Japan)","ror":"https://ror.org/04jndar25","country_code":"JP","type":"company","lineage":["https://openalex.org/I118347220"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"K. Nakayama","raw_affiliation_strings":["Nippon Electric Company Limited, Kawasaki, Miyazaki, Japan"],"affiliations":[{"raw_affiliation_string":"Nippon Electric Company Limited, Kawasaki, Miyazaki, Japan","institution_ids":["https://openalex.org/I118347220"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5059922488","display_name":"Y. Sakamura","orcid":null},"institutions":[{"id":"https://openalex.org/I118347220","display_name":"NEC (Japan)","ror":"https://ror.org/04jndar25","country_code":"JP","type":"company","lineage":["https://openalex.org/I118347220"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Y. Sakamura","raw_affiliation_strings":["Nippon Electric Company Limited, Kawasaki, Miyazaki, Japan"],"affiliations":[{"raw_affiliation_string":"Nippon Electric Company Limited, Kawasaki, Miyazaki, Japan","institution_ids":["https://openalex.org/I118347220"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5110748483","display_name":"S. Tanaka","orcid":null},"institutions":[{"id":"https://openalex.org/I118347220","display_name":"NEC (Japan)","ror":"https://ror.org/04jndar25","country_code":"JP","type":"company","lineage":["https://openalex.org/I118347220"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"S. Tanaka","raw_affiliation_strings":["Nippon Electric Company Limited, Kawasaki, Miyazaki, Japan"],"affiliations":[{"raw_affiliation_string":"Nippon Electric Company Limited, Kawasaki, Miyazaki, Japan","institution_ids":["https://openalex.org/I118347220"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5079191387"],"corresponding_institution_ids":["https://openalex.org/I118347220"],"apc_list":null,"apc_paid":null,"fwci":51.6588,"has_fulltext":false,"cited_by_count":13,"citation_normalized_percentile":{"value":0.99488418,"is_in_top_1_percent":true,"is_in_top_10_percent":true},"cited_by_percentile_year":null,"biblio":{"volume":"6","issue":null,"first_page":"644","last_page":"647"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11946","display_name":"Antenna Design and Optimization","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/2202","display_name":"Aerospace Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11946","display_name":"Antenna Design and Optimization","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/2202","display_name":"Aerospace Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10262","display_name":"Microwave Engineering and Waveguides","score":0.9926000237464905,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9835000038146973,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7201880216598511},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.6625047922134399},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.6614843606948853},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5686237812042236},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.5618616938591003},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.4538603127002716},{"id":"https://openalex.org/keywords/nmos-logic","display_name":"NMOS logic","score":0.4509890675544739},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4385956823825836},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.4384482204914093},{"id":"https://openalex.org/keywords/chipset","display_name":"Chipset","score":0.4274228811264038},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.42483511567115784},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.33006030321121216},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1500447690486908},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.14380857348442078},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.08072558045387268}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7201880216598511},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.6625047922134399},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.6614843606948853},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5686237812042236},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.5618616938591003},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.4538603127002716},{"id":"https://openalex.org/C197162436","wikidata":"https://www.wikidata.org/wiki/Q83908","display_name":"NMOS logic","level":4,"score":0.4509890675544739},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4385956823825836},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.4384482204914093},{"id":"https://openalex.org/C73431340","wikidata":"https://www.wikidata.org/wiki/Q182656","display_name":"Chipset","level":3,"score":0.4274228811264038},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.42483511567115784},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.33006030321121216},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1500447690486908},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.14380857348442078},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.08072558045387268},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/icassp.1981.1171244","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icassp.1981.1171244","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ICASSP '81. IEEE International Conference on Acoustics, Speech, and Signal Processing","raw_type":"proceedings-article"},{"id":"pmh:oai:irdb.nii.ac.jp:01288:0000252267","is_oa":true,"landing_page_url":"https://kanazawa-u.repo.nii.ac.jp/records/7910","pdf_url":null,"source":{"id":"https://openalex.org/S7407056385","display_name":"Institutional Repositories DataBase (IRDB)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I184597095","host_organization_name":"National Institute of Informatics","host_organization_lineage":["https://openalex.org/I184597095"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-nc-nd","license_id":"https://openalex.org/licenses/cc-by-nc-nd","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Proceedings of the IEEE ICASSP '81","raw_type":"conference paper"},{"id":"pmh:oai:kanazawa-u.repo.nii.ac.jp:00007910","is_oa":true,"landing_page_url":"https://kanazawa-u.repo.nii.ac.jp/?action=repository_uri&item_id=7910","pdf_url":null,"source":{"id":"https://openalex.org/S4306400882","display_name":"Kanazawa University Repository for Academic Resources (DSpace) (Kanazawa University)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I10091056","host_organization_name":"Kanazawa University","host_organization_lineage":["https://openalex.org/I10091056"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-nc-nd","license_id":"https://openalex.org/licenses/cc-by-nc-nd","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Conference Paper"}],"best_oa_location":{"id":"pmh:oai:irdb.nii.ac.jp:01288:0000252267","is_oa":true,"landing_page_url":"https://kanazawa-u.repo.nii.ac.jp/records/7910","pdf_url":null,"source":{"id":"https://openalex.org/S7407056385","display_name":"Institutional Repositories DataBase (IRDB)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I184597095","host_organization_name":"National Institute of Informatics","host_organization_lineage":["https://openalex.org/I184597095"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-nc-nd","license_id":"https://openalex.org/licenses/cc-by-nc-nd","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Proceedings of the IEEE ICASSP '81","raw_type":"conference paper"},"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.49000000953674316,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320307769","display_name":"Astellas Pharma US","ror":"https://ror.org/05pw69n24"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1670746658","https://openalex.org/W1897055341","https://openalex.org/W1983657887","https://openalex.org/W2119842186","https://openalex.org/W2128718658","https://openalex.org/W2150772480","https://openalex.org/W4234649425"],"related_works":["https://openalex.org/W2361454123","https://openalex.org/W2385247776","https://openalex.org/W2100196563","https://openalex.org/W2217098757","https://openalex.org/W2382142327","https://openalex.org/W2977359002","https://openalex.org/W2598933208","https://openalex.org/W2534400158","https://openalex.org/W2160420414","https://openalex.org/W2160989389"],"abstract_inverted_index":{"This":[0,20],"paper":[1],"describes":[2],"a":[3,11,47,64],"new":[4],"LSI":[5],"chip":[6,21],"set":[7],"developed":[8],"to":[9,33,68,84,88],"provide":[10],"simple":[12],"and":[13,31,43,61],"cost-effective":[14],"means":[15],"for":[16],"DSP":[17,38,91],"hardware":[18],"implementation.":[19],"set,":[22],"consisting":[23],"of":[24],"two":[25],"NMOS":[26],"LSIs,":[27],"contains":[28],"enough":[29],"logic":[30,55],"memory":[32],"perform":[34],"such":[35],"high":[36,48,89],"level":[37,90],"functions":[39],"as":[40],"biquad":[41],"filters":[42],"FFT":[44],"butterflies":[45],"at":[46,63],"throughput":[49],"rate,":[50],"without":[51],"any":[52],"other":[53],"external":[54],"devices.":[56],"It":[57],"employs":[58],"serial":[59],"arithmetic":[60],"operates":[62],"clock":[65],"rate":[66,74],"up":[67],"more":[69],"than":[70],"5":[71],"MHz.":[72],"Throughput":[73],"can":[75],"be":[76],"traded-off":[77],"with":[78],"processing":[79],"accuracy.":[80],"Architecture":[81],"is":[82],"designed":[83],"pursue":[85],"self-sufficient":[86],"applicability":[87],"functions,":[92],"while":[93],"retaining":[94],"generality":[95],"in":[96],"application.":[97]},"counts_by_year":[],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}
