{"id":"https://openalex.org/W2771192023","doi":"https://doi.org/10.1109/icacci.2017.8126179","title":"VLSI implementation of LNS arithmetic unit by LUT partitioning","display_name":"VLSI implementation of LNS arithmetic unit by LUT partitioning","publication_year":2017,"publication_date":"2017-09-01","ids":{"openalex":"https://openalex.org/W2771192023","doi":"https://doi.org/10.1109/icacci.2017.8126179","mag":"2771192023"},"language":"en","primary_location":{"id":"doi:10.1109/icacci.2017.8126179","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icacci.2017.8126179","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 International Conference on Advances in Computing, Communications and Informatics (ICACCI)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5111269680","display_name":"Vivek Vinod","orcid":null},"institutions":[{"id":"https://openalex.org/I81556334","display_name":"Amrita Vishwa Vidyapeetham","ror":"https://ror.org/03am10p12","country_code":"IN","type":"education","lineage":["https://openalex.org/I81556334"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"V. Vinod","raw_affiliation_strings":["Department of Electronics and Communication Engineering, Amrita University, India"],"affiliations":[{"raw_affiliation_string":"Department of Electronics and Communication Engineering, Amrita University, India","institution_ids":["https://openalex.org/I81556334"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110981147","display_name":"Kannali P C Eswar","orcid":null},"institutions":[{"id":"https://openalex.org/I81556334","display_name":"Amrita Vishwa Vidyapeetham","ror":"https://ror.org/03am10p12","country_code":"IN","type":"education","lineage":["https://openalex.org/I81556334"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"K. Eswar","raw_affiliation_strings":["Department of Electronics and Communication Engineering, Amrita University, India"],"affiliations":[{"raw_affiliation_string":"Department of Electronics and Communication Engineering, Amrita University, India","institution_ids":["https://openalex.org/I81556334"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5061587452","display_name":"P. Vishnuvardhan","orcid":"https://orcid.org/0009-0005-4736-1617"},"institutions":[{"id":"https://openalex.org/I81556334","display_name":"Amrita Vishwa Vidyapeetham","ror":"https://ror.org/03am10p12","country_code":"IN","type":"education","lineage":["https://openalex.org/I81556334"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"P. Vishnuvardhan","raw_affiliation_strings":["Department of Electronics and Communication Engineering, Amrita University, India"],"affiliations":[{"raw_affiliation_string":"Department of Electronics and Communication Engineering, Amrita University, India","institution_ids":["https://openalex.org/I81556334"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5108268971","display_name":"G. Srikanth","orcid":null},"institutions":[{"id":"https://openalex.org/I81556334","display_name":"Amrita Vishwa Vidyapeetham","ror":"https://ror.org/03am10p12","country_code":"IN","type":"education","lineage":["https://openalex.org/I81556334"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"G. Srikanth","raw_affiliation_strings":["Department of Electronics and Communication Engineering, Amrita University, India"],"affiliations":[{"raw_affiliation_string":"Department of Electronics and Communication Engineering, Amrita University, India","institution_ids":["https://openalex.org/I81556334"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5067389192","display_name":"S R Ramesh","orcid":null},"institutions":[{"id":"https://openalex.org/I81556334","display_name":"Amrita Vishwa Vidyapeetham","ror":"https://ror.org/03am10p12","country_code":"IN","type":"education","lineage":["https://openalex.org/I81556334"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"S. R. Ramesh","raw_affiliation_strings":["Department of Electronics and Communication Engineering, Amrita University, India"],"affiliations":[{"raw_affiliation_string":"Department of Electronics and Communication Engineering, Amrita University, India","institution_ids":["https://openalex.org/I81556334"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5111269680"],"corresponding_institution_ids":["https://openalex.org/I81556334"],"apc_list":null,"apc_paid":null,"fwci":0.2271,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.58186367,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"10","issue":null,"first_page":"2241","last_page":"2245"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.7713890671730042},{"id":"https://openalex.org/keywords/operand","display_name":"Operand","score":0.6828129291534424},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6690341830253601},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5940481424331665},{"id":"https://openalex.org/keywords/arithmetic-logic-unit","display_name":"Arithmetic logic unit","score":0.5712813138961792},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.560418963432312},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.5447436571121216},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.5184378623962402},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.46316421031951904},{"id":"https://openalex.org/keywords/multiplication","display_name":"Multiplication (music)","score":0.45281165838241577},{"id":"https://openalex.org/keywords/least-significant-bit","display_name":"Least significant bit","score":0.41576266288757324},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.41324660181999207},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.38641202449798584},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3678950071334839},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.18214190006256104}],"concepts":[{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.7713890671730042},{"id":"https://openalex.org/C55526617","wikidata":"https://www.wikidata.org/wiki/Q719375","display_name":"Operand","level":2,"score":0.6828129291534424},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6690341830253601},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5940481424331665},{"id":"https://openalex.org/C100276221","wikidata":"https://www.wikidata.org/wiki/Q192903","display_name":"Arithmetic logic unit","level":2,"score":0.5712813138961792},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.560418963432312},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.5447436571121216},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.5184378623962402},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.46316421031951904},{"id":"https://openalex.org/C2780595030","wikidata":"https://www.wikidata.org/wiki/Q3860309","display_name":"Multiplication (music)","level":2,"score":0.45281165838241577},{"id":"https://openalex.org/C4305246","wikidata":"https://www.wikidata.org/wiki/Q3885225","display_name":"Least significant bit","level":2,"score":0.41576266288757324},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.41324660181999207},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.38641202449798584},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3678950071334839},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.18214190006256104},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icacci.2017.8126179","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icacci.2017.8126179","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 International Conference on Advances in Computing, Communications and Informatics (ICACCI)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.550000011920929,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1467803821","https://openalex.org/W1982972110","https://openalex.org/W2001806972","https://openalex.org/W2011732387","https://openalex.org/W2012290000","https://openalex.org/W2032892910","https://openalex.org/W2045146697","https://openalex.org/W2107624728","https://openalex.org/W2127097384","https://openalex.org/W2127968466","https://openalex.org/W2153039279","https://openalex.org/W2171557561","https://openalex.org/W2566496004","https://openalex.org/W6628575332"],"related_works":["https://openalex.org/W2089343558","https://openalex.org/W1907116313","https://openalex.org/W2015084332","https://openalex.org/W2403291794","https://openalex.org/W3009603104","https://openalex.org/W2525693927","https://openalex.org/W1998028015","https://openalex.org/W2382457518","https://openalex.org/W2135151476","https://openalex.org/W2496279934"],"abstract_inverted_index":{"The":[0,50,112],"main":[1],"motto":[2],"of":[3,33,52,91,110,133],"every":[4],"electronic":[5],"industry":[6],"is":[7,18,45,94,114,123],"to":[8,15,84],"achieve":[9,16],"low":[10,30],"power.":[11],"An":[12],"efficient":[13],"way":[14],"this":[17],"by":[19,47],"adapting":[20],"different":[21],"architectural":[22],"modifications":[23],"in":[24,70,135],"the":[25,56,86,92,108,121],"design.":[26],"This":[27],"paper":[28],"proposes":[29],"power":[31,57,87,136],"implementation":[32],"Logarithmic":[34],"Number":[35],"System":[36],"(LNS)":[37],"arithmetic":[38,64],"unit":[39],"on":[40,55,101,107,125],"a":[41],"FPGA.":[42],"Power":[43],"reduction":[44,134],"achieved":[46],"partitioning":[48],"technique.":[49],"influence":[51],"partitioned":[53],"memory":[54],"dissipated":[58],"and":[59,68,79,105,120],"delay":[60],"required":[61],"for":[62],"performing":[63],"operations":[65],"like":[66],"add":[67],"sub":[69],"LNS":[71],"are":[72,82],"measured.":[73],"Two":[74],"design":[75],"parameters":[76],"namely":[77],"MSB":[78,102],"LSB":[80,104],"techniques":[81],"exploited":[83],"minimize":[85],"dissipation.":[88],"Only":[89],"one":[90],"sub-LUT":[93],"activated":[95],"upon":[96],"each":[97],"operation":[98],"which":[99],"depends":[100],"or":[103],"also":[106],"sign":[109],"operands.":[111],"synthesis":[113],"carried":[115],"out":[116],"using":[117],"Xilinx":[118],"ISE":[119],"hardware":[122],"implemented":[124],"ZYBO":[126],"Zynq-7000":[127],"development":[128],"board.":[129],"A":[130],"considerable":[131],"amount":[132],"was":[137],"obtained.":[138]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}