{"id":"https://openalex.org/W2774156717","doi":"https://doi.org/10.1109/icacci.2017.8126126","title":"Design and implementation of 8-bit vedic multiplier using mGDI technique","display_name":"Design and implementation of 8-bit vedic multiplier using mGDI technique","publication_year":2017,"publication_date":"2017-09-01","ids":{"openalex":"https://openalex.org/W2774156717","doi":"https://doi.org/10.1109/icacci.2017.8126126","mag":"2774156717"},"language":"en","primary_location":{"id":"doi:10.1109/icacci.2017.8126126","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icacci.2017.8126126","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 International Conference on Advances in Computing, Communications and Informatics (ICACCI)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5027717147","display_name":"Shashank S. Meti","orcid":null},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Shashank S. Meti","raw_affiliation_strings":["Department of ECE, R V College of Engineering, Bengaluru, India"],"affiliations":[{"raw_affiliation_string":"Department of ECE, R V College of Engineering, Bengaluru, India","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5074092008","display_name":"C. N. Bharath","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"C.N. Bharath","raw_affiliation_strings":["Department of ECE, R V College of Engineering, Bengaluru, India"],"affiliations":[{"raw_affiliation_string":"Department of ECE, R V College of Engineering, Bengaluru, India","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5033912348","display_name":"Praveen Kumar Y G","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Y.G. Praveen Kumar","raw_affiliation_strings":["Department of ECE, R V College of Engineering, Bengaluru, India"],"affiliations":[{"raw_affiliation_string":"Department of ECE, R V College of Engineering, Bengaluru, India","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5108763317","display_name":"B S Kariyappa","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"B.S. Kariyappa","raw_affiliation_strings":["Department of ECE, R V College of Engineering, Bengaluru, India"],"affiliations":[{"raw_affiliation_string":"Department of ECE, R V College of Engineering, Bengaluru, India","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5027717147"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.8741,"has_fulltext":false,"cited_by_count":14,"citation_normalized_percentile":{"value":0.76982256,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"1923","last_page":"1927"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9976000189781189,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13182","display_name":"Quantum-Dot Cellular Automata","score":0.995199978351593,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/multiplier","display_name":"Multiplier (economics)","score":0.6958339810371399},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.6876963376998901},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5936775803565979},{"id":"https://openalex.org/keywords/bit","display_name":"Bit (key)","score":0.5756828188896179},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.2678564190864563},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.09272027015686035}],"concepts":[{"id":"https://openalex.org/C124584101","wikidata":"https://www.wikidata.org/wiki/Q1053266","display_name":"Multiplier (economics)","level":2,"score":0.6958339810371399},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.6876963376998901},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5936775803565979},{"id":"https://openalex.org/C117011727","wikidata":"https://www.wikidata.org/wiki/Q1278488","display_name":"Bit (key)","level":2,"score":0.5756828188896179},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.2678564190864563},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.09272027015686035},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icacci.2017.8126126","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icacci.2017.8126126","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 International Conference on Advances in Computing, Communications and Informatics (ICACCI)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.7599999904632568,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W2050612396","https://openalex.org/W2097258441","https://openalex.org/W2119459904","https://openalex.org/W2127696501","https://openalex.org/W2314790765","https://openalex.org/W2622611104","https://openalex.org/W6674905309","https://openalex.org/W6699046764"],"related_works":["https://openalex.org/W2748952813","https://openalex.org/W2411923897","https://openalex.org/W4285347720","https://openalex.org/W4200259850","https://openalex.org/W2333831899","https://openalex.org/W2484894494","https://openalex.org/W2367385042","https://openalex.org/W4381186982","https://openalex.org/W2040781570","https://openalex.org/W4281295723"],"abstract_inverted_index":{"The":[0,103,125],"main":[1],"constraints":[2],"in":[3,26,130],"recent":[4],"trends":[5],"of":[6,29,44,95],"VLSI":[7],"technology":[8],"are":[9,40],"power,":[10],"area":[11,18],"and":[12,19,37,99,115],"delay.":[13],"CMOS":[14,123],"designs":[15],"occupy":[16],"more":[17,21],"dissipate":[20],"power.":[22],"Power":[23],"dissipation":[24],"results":[25],"heating":[27],"up":[28],"an":[30,66],"IC":[31],"which":[32],"directly":[33],"affects":[34],"the":[35,41,61],"reliability":[36],"performance.":[38],"Multipliers":[39],"integral":[42],"part":[43],"major":[45],"application":[46],"systems":[47],"like":[48],"Microprocessor,":[49],"Digital":[50],"Signal":[51],"Processor":[52],"(DSP)":[53],"etc.,":[54],"so":[55],"it":[56],"is":[57,75,86,128],"necessary":[58],"to":[59,64,121],"optimize":[60],"multiplier":[62,74,85,98,107,127],"unit":[63],"build":[65],"efficient":[67],"processor.":[68],"In":[69],"this":[70],"paper,":[71],"8-bit":[72,83],"Vedic":[73,84,97],"proposed":[76,104,126],"using":[77,88],"modified":[78],"Gate":[79],"Diffusion":[80],"Input":[81],"(mGDI).":[82],"designed":[87],"Urdhva":[89],"Tiryagbhyam":[90],"sutra":[91],"with":[92],"4":[93],"numbers":[94],"4-bit":[96],"3":[100],"adder":[101],"circuits.":[102],"mGDI":[105],"based":[106],"consumes":[108],"66%":[109],"less":[110,113,117],"area,":[111],"76.1%":[112],"power":[114],"60%":[116],"delay":[118],"when":[119],"compared":[120],"conventional":[122],"design.":[124],"implemented":[129],"cadence":[131],"virtuoso":[132],"tool":[133],"on":[134],"180nm":[135],"technology.":[136]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":3},{"year":2020,"cited_by_count":3},{"year":2019,"cited_by_count":3}],"updated_date":"2026-03-28T08:17:26.163206","created_date":"2025-10-10T00:00:00"}
