{"id":"https://openalex.org/W2771239746","doi":"https://doi.org/10.1109/icacci.2017.8126028","title":"Efficient test scheduling for reusable BIST in 3D stacked ICs","display_name":"Efficient test scheduling for reusable BIST in 3D stacked ICs","publication_year":2017,"publication_date":"2017-09-01","ids":{"openalex":"https://openalex.org/W2771239746","doi":"https://doi.org/10.1109/icacci.2017.8126028","mag":"2771239746"},"language":"en","primary_location":{"id":"doi:10.1109/icacci.2017.8126028","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icacci.2017.8126028","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 International Conference on Advances in Computing, Communications and Informatics (ICACCI)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5065301821","display_name":"Navya Mohan","orcid":"https://orcid.org/0000-0002-1224-1288"},"institutions":[{"id":"https://openalex.org/I81556334","display_name":"Amrita Vishwa Vidyapeetham","ror":"https://ror.org/03am10p12","country_code":"IN","type":"education","lineage":["https://openalex.org/I81556334"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Navya Mohan","raw_affiliation_strings":["Department of Electronics and Communication Engineering, Amrita University, INDIA"],"affiliations":[{"raw_affiliation_string":"Department of Electronics and Communication Engineering, Amrita University, INDIA","institution_ids":["https://openalex.org/I81556334"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103788622","display_name":"Maya Krishnan","orcid":null},"institutions":[{"id":"https://openalex.org/I81556334","display_name":"Amrita Vishwa Vidyapeetham","ror":"https://ror.org/03am10p12","country_code":"IN","type":"education","lineage":["https://openalex.org/I81556334"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Maya Krishnan","raw_affiliation_strings":["Department of Electronics and Communication Engineering, Amrita University, INDIA"],"affiliations":[{"raw_affiliation_string":"Department of Electronics and Communication Engineering, Amrita University, INDIA","institution_ids":["https://openalex.org/I81556334"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5057726672","display_name":"S Sachin Kumar","orcid":"https://orcid.org/0000-0002-3298-0539"},"institutions":[{"id":"https://openalex.org/I81556334","display_name":"Amrita Vishwa Vidyapeetham","ror":"https://ror.org/03am10p12","country_code":"IN","type":"education","lineage":["https://openalex.org/I81556334"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Sudhir Kumar Rai","raw_affiliation_strings":["Department of Electronics and Communication Engineering, Amrita University, INDIA"],"affiliations":[{"raw_affiliation_string":"Department of Electronics and Communication Engineering, Amrita University, INDIA","institution_ids":["https://openalex.org/I81556334"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5001678887","display_name":"M. MathuMeitha","orcid":null},"institutions":[{"id":"https://openalex.org/I81556334","display_name":"Amrita Vishwa Vidyapeetham","ror":"https://ror.org/03am10p12","country_code":"IN","type":"education","lineage":["https://openalex.org/I81556334"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"M. MathuMeitha","raw_affiliation_strings":["Department of Electronics and Communication Engineering, Amrita University, INDIA"],"affiliations":[{"raw_affiliation_string":"Department of Electronics and Communication Engineering, Amrita University, INDIA","institution_ids":["https://openalex.org/I81556334"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5017924968","display_name":"S. Sivakalyan","orcid":null},"institutions":[{"id":"https://openalex.org/I81556334","display_name":"Amrita Vishwa Vidyapeetham","ror":"https://ror.org/03am10p12","country_code":"IN","type":"education","lineage":["https://openalex.org/I81556334"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"S. Sivakalyan","raw_affiliation_strings":["Department of Electronics and Communication Engineering, Amrita University, INDIA"],"affiliations":[{"raw_affiliation_string":"Department of Electronics and Communication Engineering, Amrita University, INDIA","institution_ids":["https://openalex.org/I81556334"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5065301821"],"corresponding_institution_ids":["https://openalex.org/I81556334"],"apc_list":null,"apc_paid":null,"fwci":0.4633,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.64573679,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1349","last_page":"1355"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/built-in-self-test","display_name":"Built-in self-test","score":0.758887767791748},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.6585326194763184},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.5684525370597839},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5397319793701172},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.5214526057243347},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.5187047123908997},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5132067203521729},{"id":"https://openalex.org/keywords/schedule","display_name":"Schedule","score":0.5038561224937439},{"id":"https://openalex.org/keywords/skyline","display_name":"Skyline","score":0.44784536957740784},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.3955965042114258},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.33074578642845154}],"concepts":[{"id":"https://openalex.org/C2780980493","wikidata":"https://www.wikidata.org/wiki/Q181142","display_name":"Built-in self-test","level":2,"score":0.758887767791748},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.6585326194763184},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.5684525370597839},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5397319793701172},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.5214526057243347},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.5187047123908997},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5132067203521729},{"id":"https://openalex.org/C68387754","wikidata":"https://www.wikidata.org/wiki/Q7271585","display_name":"Schedule","level":2,"score":0.5038561224937439},{"id":"https://openalex.org/C2780757406","wikidata":"https://www.wikidata.org/wiki/Q465837","display_name":"Skyline","level":2,"score":0.44784536957740784},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.3955965042114258},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.33074578642845154},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C124101348","wikidata":"https://www.wikidata.org/wiki/Q172491","display_name":"Data mining","level":1,"score":0.0},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icacci.2017.8126028","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icacci.2017.8126028","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 International Conference on Advances in Computing, Communications and Informatics (ICACCI)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.49000000953674316}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1490400474","https://openalex.org/W1990828594","https://openalex.org/W2030841740","https://openalex.org/W2081825155","https://openalex.org/W2240990621","https://openalex.org/W2399241800","https://openalex.org/W2529670874"],"related_works":["https://openalex.org/W1994126304","https://openalex.org/W2087306197","https://openalex.org/W1973297295","https://openalex.org/W2316530548","https://openalex.org/W2505069962","https://openalex.org/W3096764880","https://openalex.org/W2039842051","https://openalex.org/W2317048282","https://openalex.org/W2150113875","https://openalex.org/W2025912852"],"abstract_inverted_index":{"VLSI":[0],"testing":[1,44,77],"is":[2,42,56,74,83,88,130],"essential":[3],"with":[4,144],"advancing":[5],"technology":[6],"as":[7,96],"it":[8],"helps":[9],"improve":[10],"yield":[11],"and":[12,31,68],"enables":[13,47],"the":[14,28,35,48,60,63,97,133,145],"detection":[15],"of":[16,37,62],"faulty":[17],"chips":[18],"after":[19],"manufacturing.":[20],"The":[21,71,128,139],"factors":[22],"which":[23,46,58,100],"play":[24],"important":[25],"roles":[26],"are":[27,94,101,142],"power":[29],"dissipation":[30],"time":[32],"taken":[33],"during":[34,103,113],"process":[36],"testing.":[38,70],"BIST,":[39],"Built-In":[40],"Self-Test":[41],"a":[43,84,118],"technique":[45],"device":[49],"to":[50,107,122],"test":[51,126],"itself.":[52],"A":[53],"reusable":[54],"BIST":[55,65,73],"proposed":[57,72],"allows":[59],"usage":[61],"same":[64,98],"for":[66,76],"pre-bond":[67,104],"post-bond":[69],"used":[75],"3D":[78,91],"stacked":[79,92],"ICs.":[80],"Test":[81],"scheduling":[82],"critical":[85],"problem":[86],"that":[87],"faced":[89],"while":[90],"ICs":[93],"tested":[95,131],"tests":[99],"performed":[102,109],"might":[105],"need":[106],"be":[108],"simultaneously":[110],"or":[111],"so":[112],"post-bond.":[114],"Here,":[115],"we":[116],"propose":[117],"modified":[119],"Skyline":[120,149],"algorithm":[121,129],"obtain":[123],"an":[124],"improved":[125],"schedule.":[127],"on":[132],"inputs":[134],"from":[135,147],"ISCAS-85":[136],"benchmark":[137],"circuits.":[138],"obtained":[140],"results":[141,146],"compared":[143],"traditional":[148],"algorithm.":[150]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2020,"cited_by_count":2}],"updated_date":"2026-03-25T13:04:00.132906","created_date":"2025-10-10T00:00:00"}
