{"id":"https://openalex.org/W1614130422","doi":"https://doi.org/10.1109/icacci.2015.7275652","title":"FSMD RTL design manipulation for clock interface abstraction","display_name":"FSMD RTL design manipulation for clock interface abstraction","publication_year":2015,"publication_date":"2015-08-01","ids":{"openalex":"https://openalex.org/W1614130422","doi":"https://doi.org/10.1109/icacci.2015.7275652","mag":"1614130422"},"language":"en","primary_location":{"id":"doi:10.1109/icacci.2015.7275652","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icacci.2015.7275652","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 International Conference on Advances in Computing, Communications and Informatics (ICACCI)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5059026162","display_name":"Syed Saif Abrar","orcid":null},"institutions":[{"id":"https://openalex.org/I111112146","display_name":"Tallinn University of Technology","ror":"https://ror.org/0443cwa12","country_code":"EE","type":"education","lineage":["https://openalex.org/I111112146"]}],"countries":["EE"],"is_corresponding":true,"raw_author_name":"Syed Saif Abrar","raw_affiliation_strings":["Tallinn University of Technology, Estonia","Tallinn University of Technology , Estonia"],"affiliations":[{"raw_affiliation_string":"Tallinn University of Technology, Estonia","institution_ids":["https://openalex.org/I111112146"]},{"raw_affiliation_string":"Tallinn University of Technology , Estonia","institution_ids":["https://openalex.org/I111112146"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5059391257","display_name":"Maksim Jenihhin","orcid":"https://orcid.org/0000-0001-8165-9592"},"institutions":[{"id":"https://openalex.org/I111112146","display_name":"Tallinn University of Technology","ror":"https://ror.org/0443cwa12","country_code":"EE","type":"education","lineage":["https://openalex.org/I111112146"]}],"countries":["EE"],"is_corresponding":false,"raw_author_name":"Maksim Jenihhin","raw_affiliation_strings":["Tallinn University of Technology, Estonia","Tallinn University of Technology , Estonia"],"affiliations":[{"raw_affiliation_string":"Tallinn University of Technology, Estonia","institution_ids":["https://openalex.org/I111112146"]},{"raw_affiliation_string":"Tallinn University of Technology , Estonia","institution_ids":["https://openalex.org/I111112146"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5010286547","display_name":"Jaan Raik","orcid":"https://orcid.org/0000-0001-8113-020X"},"institutions":[{"id":"https://openalex.org/I111112146","display_name":"Tallinn University of Technology","ror":"https://ror.org/0443cwa12","country_code":"EE","type":"education","lineage":["https://openalex.org/I111112146"]}],"countries":["EE"],"is_corresponding":false,"raw_author_name":"Jaan Raik","raw_affiliation_strings":["Tallinn University of Technology, Estonia","Tallinn University of Technology , Estonia"],"affiliations":[{"raw_affiliation_string":"Tallinn University of Technology, Estonia","institution_ids":["https://openalex.org/I111112146"]},{"raw_affiliation_string":"Tallinn University of Technology , Estonia","institution_ids":["https://openalex.org/I111112146"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5059026162"],"corresponding_institution_ids":["https://openalex.org/I111112146"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.03640624,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"463","last_page":"468"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/systemc","display_name":"SystemC","score":0.8966913223266602},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8210024833679199},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.6351141333580017},{"id":"https://openalex.org/keywords/register-transfer-level","display_name":"Register-transfer level","score":0.6126976013183594},{"id":"https://openalex.org/keywords/transaction-level-modeling","display_name":"Transaction-level modeling","score":0.6071921586990356},{"id":"https://openalex.org/keywords/abstraction","display_name":"Abstraction","score":0.5882143378257751},{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.5247635841369629},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5191227793693542},{"id":"https://openalex.org/keywords/datapath","display_name":"Datapath","score":0.5090360045433044},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5006434917449951},{"id":"https://openalex.org/keywords/electronic-system-level-design-and-verification","display_name":"Electronic system-level design and verification","score":0.49820780754089355},{"id":"https://openalex.org/keywords/hardware-description-language","display_name":"Hardware description language","score":0.4859958589076996},{"id":"https://openalex.org/keywords/abstraction-layer","display_name":"Abstraction layer","score":0.4848548173904419},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.4337228536605835},{"id":"https://openalex.org/keywords/correctness","display_name":"Correctness","score":0.422953337430954},{"id":"https://openalex.org/keywords/formal-verification","display_name":"Formal verification","score":0.42280182242393494},{"id":"https://openalex.org/keywords/finite-state-machine","display_name":"Finite-state machine","score":0.4132523536682129},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.3256210684776306},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.2786894738674164},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.27024996280670166},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.26379865407943726},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.105866938829422},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.08216282725334167}],"concepts":[{"id":"https://openalex.org/C2776928060","wikidata":"https://www.wikidata.org/wiki/Q1753563","display_name":"SystemC","level":2,"score":0.8966913223266602},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8210024833679199},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.6351141333580017},{"id":"https://openalex.org/C34854456","wikidata":"https://www.wikidata.org/wiki/Q1484552","display_name":"Register-transfer level","level":4,"score":0.6126976013183594},{"id":"https://openalex.org/C169571997","wikidata":"https://www.wikidata.org/wiki/Q966099","display_name":"Transaction-level modeling","level":3,"score":0.6071921586990356},{"id":"https://openalex.org/C124304363","wikidata":"https://www.wikidata.org/wiki/Q673661","display_name":"Abstraction","level":2,"score":0.5882143378257751},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.5247635841369629},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5191227793693542},{"id":"https://openalex.org/C2781198647","wikidata":"https://www.wikidata.org/wiki/Q1633673","display_name":"Datapath","level":2,"score":0.5090360045433044},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5006434917449951},{"id":"https://openalex.org/C77495112","wikidata":"https://www.wikidata.org/wiki/Q5358436","display_name":"Electronic system-level design and verification","level":2,"score":0.49820780754089355},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.4859958589076996},{"id":"https://openalex.org/C147358964","wikidata":"https://www.wikidata.org/wiki/Q1200992","display_name":"Abstraction layer","level":3,"score":0.4848548173904419},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.4337228536605835},{"id":"https://openalex.org/C55439883","wikidata":"https://www.wikidata.org/wiki/Q360812","display_name":"Correctness","level":2,"score":0.422953337430954},{"id":"https://openalex.org/C111498074","wikidata":"https://www.wikidata.org/wiki/Q173326","display_name":"Formal verification","level":2,"score":0.42280182242393494},{"id":"https://openalex.org/C167822520","wikidata":"https://www.wikidata.org/wiki/Q176452","display_name":"Finite-state machine","level":2,"score":0.4132523536682129},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.3256210684776306},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.2786894738674164},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.27024996280670166},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.26379865407943726},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.105866938829422},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.08216282725334167},{"id":"https://openalex.org/C111472728","wikidata":"https://www.wikidata.org/wiki/Q9471","display_name":"Epistemology","level":1,"score":0.0},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C129307140","wikidata":"https://www.wikidata.org/wiki/Q6795880","display_name":"Maximum bubble pressure method","level":3,"score":0.0},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icacci.2015.7275652","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icacci.2015.7275652","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 International Conference on Advances in Computing, Communications and Informatics (ICACCI)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/11","score":0.47999998927116394,"display_name":"Sustainable cities and communities"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W203492949","https://openalex.org/W1567363020","https://openalex.org/W1947997869","https://openalex.org/W1998879896","https://openalex.org/W2060461359","https://openalex.org/W2060589138","https://openalex.org/W2062795256","https://openalex.org/W2100194416","https://openalex.org/W2118670697","https://openalex.org/W2121161103","https://openalex.org/W2135253421","https://openalex.org/W2158068912","https://openalex.org/W2170664015","https://openalex.org/W2493328864","https://openalex.org/W2506991382","https://openalex.org/W4246084264","https://openalex.org/W6608153096","https://openalex.org/W6685340775"],"related_works":["https://openalex.org/W1525398417","https://openalex.org/W2105118350","https://openalex.org/W2035296141","https://openalex.org/W4247397443","https://openalex.org/W1831349210","https://openalex.org/W2552808814","https://openalex.org/W2143185107","https://openalex.org/W1486803855","https://openalex.org/W3124567525","https://openalex.org/W1614130422"],"abstract_inverted_index":{"The":[0,102,123,174],"rapid":[1],"raise":[2],"of":[3,14,23,30,63,157,195],"embedded":[4],"systems":[5],"design":[6,24,78,117,138,158,183],"complexity":[7],"and":[8,38,43,54,99,141,184,192],"size":[9],"has":[10,19],"emphasized":[11],"the":[12,27,47,163,171,185,196],"importance":[13],"high-performance":[15],"simulation":[16,82,172,190],"models.":[17],"This":[18],"resulted":[20],"in":[21,139,152],"emergence":[22],"methodologies":[25],"at":[26,91],"higher":[28],"levels":[29],"abstraction":[31],"such":[32,84],"as":[33,46,127],"Electronic":[34],"System":[35],"Level":[36,40,67],"(ESL)":[37],"Transaction":[39],"Modelling":[41],"(TLM)":[42],"SystemC":[44,153],"language":[45],"main":[48],"instrument.":[49],"In":[50],"practice,":[51],"system":[52,55],"architects":[53],"integrators":[56],"often":[57],"have":[58],"access":[59],"to":[60,144,169],"a":[61,110,180],"library":[62],"legacy":[64],"Register":[65],"Transfer":[66],"(RTL)":[68],"HW":[69],"IP":[70,77,86],"cores":[71,87],"or":[72],"obtain":[73],"new":[74],"ones":[75],"from":[76],"houses.":[79],"To":[80],"address":[81],"performance,":[83],"RTL":[85,116,137],"are":[88,177],"manually":[89],"recreated":[90],"more":[92],"abstract":[93],"levels,":[94],"which":[95],"implies":[96],"significant":[97],"tedious":[98],"error-prone":[100],"effort.":[101],"current":[103],"paper":[104],"addresses":[105],"this":[106],"problem":[107],"by":[108,160],"proposing":[109],"novel":[111],"approach":[112,125],"for":[113,119],"automated":[114],"FSMD":[115,130],"manipulation":[118,124,175],"clock":[120,164],"interface":[121,165],"abstraction.":[122],"takes":[126],"an":[128,145],"input":[129],"(Finite":[131],"State":[132,148],"Machine":[133,149],"with":[134,154],"datapath":[135],"embedded)":[136],"VHDL":[140],"transforms":[142],"it":[143],"equivalent":[146],"Algorithmic":[147],"(ASM)":[150],"representation":[151],"explicit":[155],"separation":[156],"functionality":[159],"states.":[161],"Finally,":[162],"is":[166],"abstracted":[167],"up":[168],"optimize":[170],"performance.":[173],"details":[176],"demonstrated":[178],"on":[179],"case":[181],"study":[182],"first":[186],"experimental":[187],"results":[188],"show":[189],"speed-up":[191],"prove":[193],"feasibility":[194],"proposed":[197],"approach.":[198]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
