{"id":"https://openalex.org/W2156077288","doi":"https://doi.org/10.1109/icacci.2015.7275650","title":"Energy efficient and high performance 64-bit Arithmetic Logic Unit using 28nm technology","display_name":"Energy efficient and high performance 64-bit Arithmetic Logic Unit using 28nm technology","publication_year":2015,"publication_date":"2015-08-01","ids":{"openalex":"https://openalex.org/W2156077288","doi":"https://doi.org/10.1109/icacci.2015.7275650","mag":"2156077288"},"language":"en","primary_location":{"id":"doi:10.1109/icacci.2015.7275650","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icacci.2015.7275650","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 International Conference on Advances in Computing, Communications and Informatics (ICACCI)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://zenodo.org/record/33245","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5090661147","display_name":"Shruti Murgai","orcid":null},"institutions":[{"id":"https://openalex.org/I191972202","display_name":"Amity University","ror":"https://ror.org/02n9z0v62","country_code":"IN","type":"education","lineage":["https://openalex.org/I191972202"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Shruti Murgai","raw_affiliation_strings":["Department of ECE ASET, AMITY University, Noida, INDIA"],"affiliations":[{"raw_affiliation_string":"Department of ECE ASET, AMITY University, Noida, INDIA","institution_ids":["https://openalex.org/I191972202"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5079400687","display_name":"Ashutosh Gupta","orcid":"https://orcid.org/0000-0002-3768-6355"},"institutions":[{"id":"https://openalex.org/I191972202","display_name":"Amity University","ror":"https://ror.org/02n9z0v62","country_code":"IN","type":"education","lineage":["https://openalex.org/I191972202"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Ashutosh Gupta","raw_affiliation_strings":["Department of ECE ASET, AMITY University, Noida, INDIA"],"affiliations":[{"raw_affiliation_string":"Department of ECE ASET, AMITY University, Noida, INDIA","institution_ids":["https://openalex.org/I191972202"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5103573238","display_name":"Gayathri Muthukrishnan","orcid":null},"institutions":[{"id":"https://openalex.org/I191972202","display_name":"Amity University","ror":"https://ror.org/02n9z0v62","country_code":"IN","type":"education","lineage":["https://openalex.org/I191972202"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Gayathri Muthukrishnan","raw_affiliation_strings":["Department of ECE ASET, AMITY University, Noida, INDIA"],"affiliations":[{"raw_affiliation_string":"Department of ECE ASET, AMITY University, Noida, INDIA","institution_ids":["https://openalex.org/I191972202"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5090661147"],"corresponding_institution_ids":["https://openalex.org/I191972202"],"apc_list":null,"apc_paid":null,"fwci":2.202,"has_fulltext":false,"cited_by_count":11,"citation_normalized_percentile":{"value":0.88981962,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":97,"max":99},"biblio":{"volume":"5","issue":null,"first_page":"453","last_page":"456"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13182","display_name":"Quantum-Dot Cellular Automata","score":0.995199978351593,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10682","display_name":"Quantum Computing Algorithms and Architecture","score":0.9925000071525574,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.787895143032074},{"id":"https://openalex.org/keywords/arithmetic-logic-unit","display_name":"Arithmetic logic unit","score":0.7029979825019836},{"id":"https://openalex.org/keywords/bit","display_name":"Bit (key)","score":0.6224297285079956},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6102622747421265},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5203706622123718},{"id":"https://openalex.org/keywords/unit","display_name":"Unit (ring theory)","score":0.516767144203186},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.5057134628295898},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.4172937572002411},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.32593005895614624},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.24160155653953552},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.2308540642261505},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.22774767875671387},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.1800042986869812},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1745491623878479},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.10800626873970032}],"concepts":[{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.787895143032074},{"id":"https://openalex.org/C100276221","wikidata":"https://www.wikidata.org/wiki/Q192903","display_name":"Arithmetic logic unit","level":2,"score":0.7029979825019836},{"id":"https://openalex.org/C117011727","wikidata":"https://www.wikidata.org/wiki/Q1278488","display_name":"Bit (key)","level":2,"score":0.6224297285079956},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6102622747421265},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5203706622123718},{"id":"https://openalex.org/C122637931","wikidata":"https://www.wikidata.org/wiki/Q118084","display_name":"Unit (ring theory)","level":2,"score":0.516767144203186},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.5057134628295898},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.4172937572002411},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.32593005895614624},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.24160155653953552},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2308540642261505},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.22774767875671387},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.1800042986869812},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1745491623878479},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.10800626873970032},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0},{"id":"https://openalex.org/C145420912","wikidata":"https://www.wikidata.org/wiki/Q853077","display_name":"Mathematics education","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/icacci.2015.7275650","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icacci.2015.7275650","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 International Conference on Advances in Computing, Communications and Informatics (ICACCI)","raw_type":"proceedings-article"},{"id":"pmh:oai:zenodo.org:33245","is_oa":true,"landing_page_url":"https://zenodo.org/record/33245","pdf_url":null,"source":{"id":"https://openalex.org/S4306400562","display_name":"Zenodo (CERN European Organization for Nuclear Research)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I67311998","host_organization_name":"European Organization for Nuclear Research","host_organization_lineage":["https://openalex.org/I67311998"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/conferencePaper"}],"best_oa_location":{"id":"pmh:oai:zenodo.org:33245","is_oa":true,"landing_page_url":"https://zenodo.org/record/33245","pdf_url":null,"source":{"id":"https://openalex.org/S4306400562","display_name":"Zenodo (CERN European Organization for Nuclear Research)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I67311998","host_organization_name":"European Organization for Nuclear Research","host_organization_lineage":["https://openalex.org/I67311998"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/conferencePaper"},"sustainable_development_goals":[{"score":0.8999999761581421,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1505085315","https://openalex.org/W1926390349","https://openalex.org/W1998265329","https://openalex.org/W2018290821","https://openalex.org/W2023849526","https://openalex.org/W2071949830","https://openalex.org/W2118648473","https://openalex.org/W2141973218","https://openalex.org/W2220115126","https://openalex.org/W2320075946","https://openalex.org/W2557138176","https://openalex.org/W4285719527","https://openalex.org/W6688413558","https://openalex.org/W6730019939"],"related_works":["https://openalex.org/W2098419840","https://openalex.org/W2526300902","https://openalex.org/W2112701087","https://openalex.org/W2121963733","https://openalex.org/W1985308002","https://openalex.org/W2542337934","https://openalex.org/W2170504327","https://openalex.org/W2043019798","https://openalex.org/W1977171228","https://openalex.org/W2129707489"],"abstract_inverted_index":{"Arithmetic":[0,27],"Logic":[1,29],"Units":[2],"are":[3],"one":[4],"of":[5,16,34,54,67,91],"the":[6,32,47,80],"vital":[7],"unit":[8],"in":[9,49,52,65,72,89,115,138,158],"general":[10],"purpose":[11],"processors":[12],"and":[13,28,56,93,99,108,141],"major":[14],"source":[15],"power":[17,55,68,92,98,101],"dissipation.":[18],"In":[19,58],"this":[20,59],"paper":[21],"we":[22],"have":[23,43],"demonstrated":[24],"an":[25,35],"optimized":[26,36,64],"Unit":[30],"through":[31,131],"use":[33],"carry":[37,75],"select":[38,41,76],"adder.":[39,77],"Carry":[40],"adders":[42],"been":[44,70,103,121,126,144],"considered":[45],"as":[46],"best":[48],"their":[50],"category":[51],"terms":[53,66,90],"delay.":[57,94],"context":[60],"a":[61,74,86],"full":[62],"adder":[63,82],"has":[69,102,119,125,143],"used":[71],"synthesizing":[73],"Combined":[78],"with":[79],"new":[81],"structure,":[83],"there":[84],"is":[85,151],"substantial":[87],"improvement":[88],"The":[95,123,149],"total":[96,116],"device":[97],"hierarchy":[100],"reduced":[104],"to":[105],"12.5":[106],"%":[107,110,113],"53.39":[109],"respectively.":[111],"3":[112],"reduction":[114],"completion":[117],"time":[118],"also":[120],"observed.":[122],"circuit":[124],"synthesized":[127],"on":[128,146,156],"kintex":[129],"FPGA":[130],"Xilinx":[132],"14.3":[133],"using":[134,153],"28":[135],"nm":[136],"technology":[137],"Verilog":[139,155],"HDL":[140],"results":[142],"simulated":[145],"Modelsim":[147],"10.3c.":[148],"design":[150],"verified":[152],"System":[154],"QuestaSim":[157],"UVM":[159],"environment.":[160]},"counts_by_year":[{"year":2017,"cited_by_count":4},{"year":2016,"cited_by_count":7}],"updated_date":"2026-03-20T23:20:44.827607","created_date":"2025-10-10T00:00:00"}
