{"id":"https://openalex.org/W2071546041","doi":"https://doi.org/10.1109/icacci.2014.6968327","title":"Efficient system level cache architecture for multimedia SoC","display_name":"Efficient system level cache architecture for multimedia SoC","publication_year":2014,"publication_date":"2014-09-01","ids":{"openalex":"https://openalex.org/W2071546041","doi":"https://doi.org/10.1109/icacci.2014.6968327","mag":"2071546041"},"language":"en","primary_location":{"id":"doi:10.1109/icacci.2014.6968327","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icacci.2014.6968327","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 International Conference on Advances in Computing, Communications and Informatics (ICACCI)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5025210690","display_name":"Prashant Karandikar","orcid":null},"institutions":[{"id":"https://openalex.org/I74760111","display_name":"Texas Instruments (United States)","ror":"https://ror.org/03vsmv677","country_code":"US","type":"company","lineage":["https://openalex.org/I74760111"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Prashant Karandikar","raw_affiliation_strings":["Embedded Processor BU, Texas Instruments Inc, Bangalore, India"],"affiliations":[{"raw_affiliation_string":"Embedded Processor BU, Texas Instruments Inc, Bangalore, India","institution_ids":["https://openalex.org/I74760111"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5044937170","display_name":"Mihir Mody","orcid":null},"institutions":[{"id":"https://openalex.org/I74760111","display_name":"Texas Instruments (United States)","ror":"https://ror.org/03vsmv677","country_code":"US","type":"company","lineage":["https://openalex.org/I74760111"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Mihir Mody","raw_affiliation_strings":["Embedded Processor BU, Texas Instruments Inc, Bangalore, India"],"affiliations":[{"raw_affiliation_string":"Embedded Processor BU, Texas Instruments Inc, Bangalore, India","institution_ids":["https://openalex.org/I74760111"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5064188494","display_name":"Hetul Sanghvi","orcid":null},"institutions":[{"id":"https://openalex.org/I74760111","display_name":"Texas Instruments (United States)","ror":"https://ror.org/03vsmv677","country_code":"US","type":"company","lineage":["https://openalex.org/I74760111"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Hetul Sanghvi","raw_affiliation_strings":["Embedded Processor BU, Texas Instruments Inc, Bangalore, India"],"affiliations":[{"raw_affiliation_string":"Embedded Processor BU, Texas Instruments Inc, Bangalore, India","institution_ids":["https://openalex.org/I74760111"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5013399549","display_name":"Vasant Easwaran","orcid":null},"institutions":[{"id":"https://openalex.org/I74760111","display_name":"Texas Instruments (United States)","ror":"https://ror.org/03vsmv677","country_code":"US","type":"company","lineage":["https://openalex.org/I74760111"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Vasant Easwaran","raw_affiliation_strings":["Embedded Processor BU, Texas Instruments Inc, Bangalore, India"],"affiliations":[{"raw_affiliation_string":"Embedded Processor BU, Texas Instruments Inc, Bangalore, India","institution_ids":["https://openalex.org/I74760111"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5074447229","display_name":"Prithvi Shankar Y A","orcid":null},"institutions":[{"id":"https://openalex.org/I74760111","display_name":"Texas Instruments (United States)","ror":"https://ror.org/03vsmv677","country_code":"US","type":"company","lineage":["https://openalex.org/I74760111"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Prithvi Shankar Y A","raw_affiliation_strings":["Embedded Processor BU, Texas Instruments Inc, Bangalore, India"],"affiliations":[{"raw_affiliation_string":"Embedded Processor BU, Texas Instruments Inc, Bangalore, India","institution_ids":["https://openalex.org/I74760111"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5066988351","display_name":"Rahul Gulati","orcid":null},"institutions":[{"id":"https://openalex.org/I74760111","display_name":"Texas Instruments (United States)","ror":"https://ror.org/03vsmv677","country_code":"US","type":"company","lineage":["https://openalex.org/I74760111"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Rahul Gulati","raw_affiliation_strings":["Embedded Processor BU, Texas Instruments Inc, Bangalore, India"],"affiliations":[{"raw_affiliation_string":"Embedded Processor BU, Texas Instruments Inc, Bangalore, India","institution_ids":["https://openalex.org/I74760111"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5017947135","display_name":"Niraj Nandan","orcid":null},"institutions":[{"id":"https://openalex.org/I74760111","display_name":"Texas Instruments (United States)","ror":"https://ror.org/03vsmv677","country_code":"US","type":"company","lineage":["https://openalex.org/I74760111"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Niraj Nandan","raw_affiliation_strings":["Embedded Processor BU, Texas Instruments Inc, Bangalore, India"],"affiliations":[{"raw_affiliation_string":"Embedded Processor BU, Texas Instruments Inc, Bangalore, India","institution_ids":["https://openalex.org/I74760111"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5000276780","display_name":"Subrangshu Das","orcid":null},"institutions":[{"id":"https://openalex.org/I74760111","display_name":"Texas Instruments (United States)","ror":"https://ror.org/03vsmv677","country_code":"US","type":"company","lineage":["https://openalex.org/I74760111"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Subrangshu Das","raw_affiliation_strings":["Embedded Processor BU, Texas Instruments Inc, Bangalore, India"],"affiliations":[{"raw_affiliation_string":"Embedded Processor BU, Texas Instruments Inc, Bangalore, India","institution_ids":["https://openalex.org/I74760111"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":8,"corresponding_author_ids":["https://openalex.org/A5025210690"],"corresponding_institution_ids":["https://openalex.org/I74760111"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.12950151,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"635","last_page":"639"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9980000257492065,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10741","display_name":"Video Coding and Compression Technologies","score":0.9972000122070312,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8885946273803711},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.7536101341247559},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.5796211957931519},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5654648542404175},{"id":"https://openalex.org/keywords/smart-cache","display_name":"Smart Cache","score":0.49145781993865967},{"id":"https://openalex.org/keywords/memory-bandwidth","display_name":"Memory bandwidth","score":0.48233911395072937},{"id":"https://openalex.org/keywords/cache-pollution","display_name":"Cache pollution","score":0.465109646320343},{"id":"https://openalex.org/keywords/cache-coloring","display_name":"Cache coloring","score":0.4627758264541626},{"id":"https://openalex.org/keywords/page-cache","display_name":"Page cache","score":0.4500924050807953},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.4466724395751953},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.4464065730571747},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3878318667411804},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.3586735129356384},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3433535695075989},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.32945114374160767}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8885946273803711},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.7536101341247559},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.5796211957931519},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5654648542404175},{"id":"https://openalex.org/C167713795","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"Smart Cache","level":5,"score":0.49145781993865967},{"id":"https://openalex.org/C188045654","wikidata":"https://www.wikidata.org/wiki/Q17148339","display_name":"Memory bandwidth","level":2,"score":0.48233911395072937},{"id":"https://openalex.org/C113166858","wikidata":"https://www.wikidata.org/wiki/Q5015981","display_name":"Cache pollution","level":5,"score":0.465109646320343},{"id":"https://openalex.org/C201148951","wikidata":"https://www.wikidata.org/wiki/Q5015976","display_name":"Cache coloring","level":4,"score":0.4627758264541626},{"id":"https://openalex.org/C36340418","wikidata":"https://www.wikidata.org/wiki/Q7124288","display_name":"Page cache","level":5,"score":0.4500924050807953},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.4466724395751953},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.4464065730571747},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3878318667411804},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.3586735129356384},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3433535695075989},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.32945114374160767},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icacci.2014.6968327","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icacci.2014.6968327","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 International Conference on Advances in Computing, Communications and Informatics (ICACCI)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.4099999964237213}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W2026945977","https://openalex.org/W2059454146","https://openalex.org/W2090879417","https://openalex.org/W2137418668","https://openalex.org/W2184017385","https://openalex.org/W6657054951","https://openalex.org/W6680611984","https://openalex.org/W6686482776"],"related_works":["https://openalex.org/W2133489088","https://openalex.org/W2118932116","https://openalex.org/W2114386333","https://openalex.org/W2535115842","https://openalex.org/W2396934146","https://openalex.org/W2363769136","https://openalex.org/W2126408955","https://openalex.org/W2006655698","https://openalex.org/W2148571123","https://openalex.org/W2734782074"],"abstract_inverted_index":{"A":[0],"typical":[1],"multimedia":[2,51,66],"SoC":[3],"consists":[4],"of":[5,24,44,70,109],"hardware":[6,123],"components":[7,26],"for":[8,30,50,65,118,134],"image":[9],"capture":[10],"&":[11],"processing,":[12],"video":[13,135],"compression":[14],"and":[15,20,28,74,91],"de-compression,":[16],"computer":[17],"vision,":[18],"graphics":[19],"display":[21],"processing.":[22],"Each":[23],"these":[25],"access":[27],"compete":[29],"the":[31,36],"limited":[32],"bandwidth":[33,72,133],"available":[34],"in":[35,68,131],"shared":[37],"external":[38],"DDR":[39,71,132],"memory.":[40],"The":[41,77,94,103,125],"traditional":[42],"solution":[43],"using":[45,100],"cache":[46,60,79,90,96,111],"is":[47,63,98],"not":[48],"suitable":[49],"traffic.":[52,137],"In":[53],"this":[54,110],"paper,":[55],"we":[56],"propose":[57],"a":[58],"novel":[59],"architecture":[61,80,97,112],"which":[62],"beneficial":[64],"traffic":[67],"terms":[69],"savings":[73],"latency":[75],"reduction.":[76],"proposed":[78,95],"uses":[81],"qualifier":[82],"based":[83],"splitter,":[84],"multiple":[85],"fully":[86],"associative":[87],"configurable":[88],"features":[89],"an":[92,114],"arbiter.":[93],"evaluated":[99],"architectural":[101],"model.":[102],"paper":[104],"also":[105],"proposes":[106],"newer":[107],"applications":[108],"as":[113],"infinite":[115],"circular":[116],"buffer":[117,120],"data":[119],"sharing":[121],"across":[122],"components.":[124],"simulation":[126],"results":[127],"show":[128],"50%":[129],"improvement":[130],"decoder":[136]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
