{"id":"https://openalex.org/W2067691498","doi":"https://doi.org/10.1109/icacci.2013.6637376","title":"Computer aided partitioning for design of parallel testable VLSI systems","display_name":"Computer aided partitioning for design of parallel testable VLSI systems","publication_year":2013,"publication_date":"2013-08-01","ids":{"openalex":"https://openalex.org/W2067691498","doi":"https://doi.org/10.1109/icacci.2013.6637376","mag":"2067691498"},"language":"en","primary_location":{"id":"doi:10.1109/icacci.2013.6637376","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icacci.2013.6637376","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 International Conference on Advances in Computing, Communications and Informatics (ICACCI)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5102796862","display_name":"Deepa Jose","orcid":"https://orcid.org/0000-0002-6347-9384"},"institutions":[{"id":"https://openalex.org/I33585257","display_name":"Anna University, Chennai","ror":"https://ror.org/01qhf1r47","country_code":"IN","type":"education","lineage":["https://openalex.org/I33585257"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Deepa Jose","raw_affiliation_strings":["Department of Electronics and Communication, College of Engineering, Anna University, Chennai, India","Dept. of Electron. & Commun., Anna Univ., Chennai, India"],"affiliations":[{"raw_affiliation_string":"Department of Electronics and Communication, College of Engineering, Anna University, Chennai, India","institution_ids":["https://openalex.org/I33585257"]},{"raw_affiliation_string":"Dept. of Electron. & Commun., Anna Univ., Chennai, India","institution_ids":["https://openalex.org/I33585257"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111881316","display_name":"P. Nirmal Kumar","orcid":null},"institutions":[{"id":"https://openalex.org/I33585257","display_name":"Anna University, Chennai","ror":"https://ror.org/01qhf1r47","country_code":"IN","type":"education","lineage":["https://openalex.org/I33585257"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"P. Nirmal Kumar","raw_affiliation_strings":["Department of Electronics and Communication, College of Engineering, Anna University, Chennai, India","Dept. of Electron. & Commun., Anna Univ., Chennai, India"],"affiliations":[{"raw_affiliation_string":"Department of Electronics and Communication, College of Engineering, Anna University, Chennai, India","institution_ids":["https://openalex.org/I33585257"]},{"raw_affiliation_string":"Dept. of Electron. & Commun., Anna Univ., Chennai, India","institution_ids":["https://openalex.org/I33585257"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5074060661","display_name":"L. Saravakanthan","orcid":null},"institutions":[{"id":"https://openalex.org/I33585257","display_name":"Anna University, Chennai","ror":"https://ror.org/01qhf1r47","country_code":"IN","type":"education","lineage":["https://openalex.org/I33585257"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"L. Saravakanthan","raw_affiliation_strings":["Department of Electronics and Communication, College of Engineering, Anna University, Chennai, India","Dept. of Electron. & Commun., Anna Univ., Chennai, India"],"affiliations":[{"raw_affiliation_string":"Department of Electronics and Communication, College of Engineering, Anna University, Chennai, India","institution_ids":["https://openalex.org/I33585257"]},{"raw_affiliation_string":"Dept. of Electron. & Commun., Anna Univ., Chennai, India","institution_ids":["https://openalex.org/I33585257"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5045331283","display_name":"R. Dheeraj","orcid":null},"institutions":[{"id":"https://openalex.org/I33585257","display_name":"Anna University, Chennai","ror":"https://ror.org/01qhf1r47","country_code":"IN","type":"education","lineage":["https://openalex.org/I33585257"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"R. Dheeraj","raw_affiliation_strings":["Department of Electronics and Communication, College of Engineering, Anna University, Chennai, India","Dept. of Electron. & Commun., Anna Univ., Chennai, India"],"affiliations":[{"raw_affiliation_string":"Department of Electronics and Communication, College of Engineering, Anna University, Chennai, India","institution_ids":["https://openalex.org/I33585257"]},{"raw_affiliation_string":"Dept. of Electron. & Commun., Anna Univ., Chennai, India","institution_ids":["https://openalex.org/I33585257"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5102796862"],"corresponding_institution_ids":["https://openalex.org/I33585257"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":12,"citation_normalized_percentile":{"value":0.12748862,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"1363","last_page":"1366"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.9079461097717285},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6897086501121521},{"id":"https://openalex.org/keywords/testability","display_name":"Testability","score":0.6417986750602722},{"id":"https://openalex.org/keywords/electronic-design-automation","display_name":"Electronic design automation","score":0.5535467863082886},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.5441007614135742},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.4826272428035736},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4688250720500946},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.43897897005081177},{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.42675644159317017},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.41592225432395935},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.32726675271987915},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.2567760944366455},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.2292611002922058},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1688438355922699},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.1623326539993286}],"concepts":[{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.9079461097717285},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6897086501121521},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.6417986750602722},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.5535467863082886},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.5441007614135742},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.4826272428035736},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4688250720500946},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.43897897005081177},{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.42675644159317017},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.41592225432395935},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.32726675271987915},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.2567760944366455},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.2292611002922058},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1688438355922699},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.1623326539993286},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icacci.2013.6637376","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icacci.2013.6637376","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 International Conference on Advances in Computing, Communications and Informatics (ICACCI)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.5699999928474426,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1483017465","https://openalex.org/W2043362541","https://openalex.org/W2105020400","https://openalex.org/W2115599064","https://openalex.org/W2136619957","https://openalex.org/W2137636909","https://openalex.org/W2154805642","https://openalex.org/W2156213030","https://openalex.org/W2158377886","https://openalex.org/W4256365432"],"related_works":["https://openalex.org/W2149827500","https://openalex.org/W2107525390","https://openalex.org/W2157191248","https://openalex.org/W2150046587","https://openalex.org/W2164493372","https://openalex.org/W2114980936","https://openalex.org/W1594445436","https://openalex.org/W2128920253","https://openalex.org/W2142405811","https://openalex.org/W2164349885"],"abstract_inverted_index":{"Design":[0],"automation":[1],"is":[2,58,102,145],"a":[3,61,136],"challenge":[4],"for":[5,90,121],"tool":[6,89,109],"designers,":[7],"due":[8],"to":[9,69],"increasing":[10],"complexity":[11],"of":[12,28,53,76,115,127,142],"building":[13],"VLSI":[14,29,54,77,87,100],"circuits":[15,94],"with":[16,60],"molecular":[17],"and":[18,38,73,104,118,134],"nano-scale":[19],"precision.":[20],"Recent":[21],"emerging":[22],"complex":[23],"problems":[24],"in":[25,50,64,139],"the":[26,36,51,71,80,112,128,140],"field":[27,52],"design":[30,55,88,113],"can":[31,96,110],"be":[32],"easily":[33],"solved":[34],"through":[35],"divide":[37],"conquer":[39],"approach":[40],"using":[41],"partitioning":[42,45,91,133],"methods.":[43],"Although,":[44],"problem":[46],"has":[47],"major":[48],"importance":[49],"automation,":[56],"it":[57],"treated":[59],"testing":[62],"perspective":[63],"this":[65],"paper.":[66],"This":[67,106],"facilitates":[68],"address":[70],"reliability":[72],"testability":[74],"issues":[75],"systems":[78],"during":[79],"early":[81],"product":[82],"development":[83],"stages.":[84],"An":[85],"automated":[86],"combinational":[92],"CMOS":[93],"that":[95],"create":[97],"parallel":[98],"testable":[99],"circuits,":[101],"developed":[103],"discussed.":[105],"computer":[107],"aided":[108],"optimize":[111],"constraints":[114],"test":[116,143],"time":[117],"hardware":[119],"overhead":[120],"design-for-testability":[122],"(DFT)":[123],"by":[124],"an":[125],"exploration":[126],"solution":[129],"search":[130],"space.":[131],"After":[132],"optimization,":[135],"considerable":[137],"reduction":[138],"length":[141],"vectors":[144],"obtained.":[146]},"counts_by_year":[{"year":2023,"cited_by_count":11},{"year":2019,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}