{"id":"https://openalex.org/W1994647026","doi":"https://doi.org/10.1109/icacci.2013.6637373","title":"Reconfigurable digital sequential system on chip design with its analysis of various parameters &amp;amp; power reduction using dynamic partial reconfiguration","display_name":"Reconfigurable digital sequential system on chip design with its analysis of various parameters &amp;amp; power reduction using dynamic partial reconfiguration","publication_year":2013,"publication_date":"2013-08-01","ids":{"openalex":"https://openalex.org/W1994647026","doi":"https://doi.org/10.1109/icacci.2013.6637373","mag":"1994647026"},"language":"en","primary_location":{"id":"doi:10.1109/icacci.2013.6637373","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icacci.2013.6637373","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 International Conference on Advances in Computing, Communications and Informatics (ICACCI)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5039767269","display_name":"Navneet Agrawal","orcid":"https://orcid.org/0000-0002-4467-0503"},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Navneet Agrawal","raw_affiliation_strings":["Department of ECE, CTAE, Udaipur, India","Dept. of ECE, CTAE, Udaipur, India"],"affiliations":[{"raw_affiliation_string":"Department of ECE, CTAE, Udaipur, India","institution_ids":[]},{"raw_affiliation_string":"Dept. of ECE, CTAE, Udaipur, India","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5074780997","display_name":"Mayuri Jain","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Mayuri Jain","raw_affiliation_strings":["Department of ECE, CTAE, Udaipur, India","Dept. of ECE, CTAE, Udaipur, India"],"affiliations":[{"raw_affiliation_string":"Department of ECE, CTAE, Udaipur, India","institution_ids":[]},{"raw_affiliation_string":"Dept. of ECE, CTAE, Udaipur, India","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5039767269"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.06999375,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1346","last_page":"1351"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9825999736785889,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9825999736785889,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9606000185012817,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.949999988079071,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/control-reconfiguration","display_name":"Control reconfiguration","score":0.8296079635620117},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.721062183380127},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.6716108322143555},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6416109800338745},{"id":"https://openalex.org/keywords/router","display_name":"Router","score":0.594818115234375},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5535458326339722},{"id":"https://openalex.org/keywords/dynamic-demand","display_name":"Dynamic demand","score":0.5182785391807556},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.5050533413887024},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.4594692885875702},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.4101048409938812},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.36305809020996094},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.31458228826522827},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.10734608769416809}],"concepts":[{"id":"https://openalex.org/C119701452","wikidata":"https://www.wikidata.org/wiki/Q5165881","display_name":"Control reconfiguration","level":2,"score":0.8296079635620117},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.721062183380127},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.6716108322143555},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6416109800338745},{"id":"https://openalex.org/C2775896111","wikidata":"https://www.wikidata.org/wiki/Q642560","display_name":"Router","level":2,"score":0.594818115234375},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5535458326339722},{"id":"https://openalex.org/C45872418","wikidata":"https://www.wikidata.org/wiki/Q5318966","display_name":"Dynamic demand","level":3,"score":0.5182785391807556},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.5050533413887024},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.4594692885875702},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.4101048409938812},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.36305809020996094},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.31458228826522827},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.10734608769416809},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icacci.2013.6637373","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icacci.2013.6637373","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 International Conference on Advances in Computing, Communications and Informatics (ICACCI)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8899999856948853,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":3,"referenced_works":["https://openalex.org/W310834548","https://openalex.org/W2125612798","https://openalex.org/W6610962169"],"related_works":["https://openalex.org/W2122026593","https://openalex.org/W2383333355","https://openalex.org/W2144353363","https://openalex.org/W2389325540","https://openalex.org/W3011158618","https://openalex.org/W2381710881","https://openalex.org/W2377412115","https://openalex.org/W567982934","https://openalex.org/W2384838054","https://openalex.org/W2374832222"],"abstract_inverted_index":{"In":[0],"this":[1],"paper,":[2],"we":[3,76,95],"have":[4,96],"designed":[5],"a":[6],"Reconfigurable":[7,32,59,117],"Digital":[8],"Sequential":[9],"System":[10],"on":[11,121,132,172],"Chip":[12],"design":[13,46,174],"capable":[14],"of":[15,39,48,63,85,90],"transmitting":[16],"and":[17,93,105,110,128,154,168,170],"receiving":[18],"data":[19,37,108],"in":[20,22,67,166],"parallel":[21],"8":[23],"bits":[24,27],"to":[25,34,42,136,141,157],"512":[26],"range.":[28],"This":[29],"circuit":[30,69,92,163],"provides":[31],"point":[33,35],"communication,":[36],"rate":[38,109],"1.54":[40],"Gbits/sec":[41],"277":[43],"Gbits/sec.":[44],"The":[45,161],"comprises":[47],"two":[49],"Sub":[50],"Circuits:":[51],"Transmitter/Receiver":[52],"&":[53],"Router.":[54],"Our":[55],"objective":[56],"after":[57,78],"developing":[58],"system":[60],"was":[61],"reduction":[62],"the":[64,68,86,91,98,116,122,150,158],"power":[65,88],"consumption":[66,89],"by":[70,113,126],"exploiting":[71],"Dynamic":[72],"Partial":[73],"Reconfiguration,":[74],"which":[75],"get":[77],"results":[79],"is":[80,149,164],"nearly":[81],"5%":[82],"-":[83],"10%":[84],"total":[87],"finally":[94,129],"concluded":[97],"calculated":[99],"parameters":[100],"i.e.":[101],"Power":[102],"Consumption":[103],"(Static":[104],"Dynamic),":[106],"Delay,":[107],"Resources":[111],"Utilized":[112],"taking":[114],"all":[115],"Transreciever":[118],"as":[119,135,144,146],"platform":[120],"various":[123],"FPGA":[124],"families":[125],"Xilinx":[127,173],"plot":[130],"them":[131],"graph,":[133],"so":[134],"exploit":[137],"respective":[138],"family":[139,155],"according":[140,156],"application,":[142],"specification":[143],"well":[145],"constraints":[147],"what":[148],"best":[151],"chosen":[152],"parameter":[153],"analysis":[159],"made.":[160],"complete":[162],"programmed":[165],"VHDL,":[167],"synthesized":[169],"simulated":[171],"suite":[175],"14.4":[176],"ISE.":[177]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
