{"id":"https://openalex.org/W1995305232","doi":"https://doi.org/10.1109/icacci.2013.6637290","title":"A multi parametric optimization based novel approach for an efficient design space exploration for ASIC design","display_name":"A multi parametric optimization based novel approach for an efficient design space exploration for ASIC design","publication_year":2013,"publication_date":"2013-08-01","ids":{"openalex":"https://openalex.org/W1995305232","doi":"https://doi.org/10.1109/icacci.2013.6637290","mag":"1995305232"},"language":"en","primary_location":{"id":"doi:10.1109/icacci.2013.6637290","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icacci.2013.6637290","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 International Conference on Advances in Computing, Communications and Informatics (ICACCI)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5047071570","display_name":"Tulasi Krishna Parvathaneni","orcid":null},"institutions":[{"id":"https://openalex.org/I876193797","display_name":"Vellore Institute of Technology University","ror":"https://ror.org/00qzypv28","country_code":"IN","type":"education","lineage":["https://openalex.org/I876193797"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Tulasi Krishna Parvathaneni","raw_affiliation_strings":["VIT University Chennai India"],"affiliations":[{"raw_affiliation_string":"VIT University Chennai India","institution_ids":["https://openalex.org/I876193797"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5029970612","display_name":"Priyam Sachdeva","orcid":null},"institutions":[{"id":"https://openalex.org/I876193797","display_name":"Vellore Institute of Technology University","ror":"https://ror.org/00qzypv28","country_code":"IN","type":"education","lineage":["https://openalex.org/I876193797"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Priyam Sachdeva","raw_affiliation_strings":["VIT University, Chennai, INDIA","VIT University Chennai India"],"affiliations":[{"raw_affiliation_string":"VIT University, Chennai, INDIA","institution_ids":["https://openalex.org/I876193797"]},{"raw_affiliation_string":"VIT University Chennai India","institution_ids":["https://openalex.org/I876193797"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5061411385","display_name":"Suraj Kumar Dhanuka","orcid":null},"institutions":[{"id":"https://openalex.org/I876193797","display_name":"Vellore Institute of Technology University","ror":"https://ror.org/00qzypv28","country_code":"IN","type":"education","lineage":["https://openalex.org/I876193797"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Suraj Kumar Dhanuka","raw_affiliation_strings":["VIT University, Chennai, INDIA","VIT University Chennai India"],"affiliations":[{"raw_affiliation_string":"VIT University, Chennai, INDIA","institution_ids":["https://openalex.org/I876193797"]},{"raw_affiliation_string":"VIT University Chennai India","institution_ids":["https://openalex.org/I876193797"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5039901063","display_name":"Mohit Gagrani","orcid":null},"institutions":[{"id":"https://openalex.org/I876193797","display_name":"Vellore Institute of Technology University","ror":"https://ror.org/00qzypv28","country_code":"IN","type":"education","lineage":["https://openalex.org/I876193797"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Mohit Gagrani","raw_affiliation_strings":["VIT University, Chennai, INDIA","VIT University Chennai India"],"affiliations":[{"raw_affiliation_string":"VIT University, Chennai, INDIA","institution_ids":["https://openalex.org/I876193797"]},{"raw_affiliation_string":"VIT University Chennai India","institution_ids":["https://openalex.org/I876193797"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5114672763","display_name":"Pallabi Sarkar","orcid":null},"institutions":[{"id":"https://openalex.org/I876193797","display_name":"Vellore Institute of Technology University","ror":"https://ror.org/00qzypv28","country_code":"IN","type":"education","lineage":["https://openalex.org/I876193797"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Pallabi Sarkar","raw_affiliation_strings":["VIT University, Chennai, INDIA","VIT University Chennai India"],"affiliations":[{"raw_affiliation_string":"VIT University, Chennai, INDIA","institution_ids":["https://openalex.org/I876193797"]},{"raw_affiliation_string":"VIT University Chennai India","institution_ids":["https://openalex.org/I876193797"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5047071570"],"corresponding_institution_ids":["https://openalex.org/I876193797"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.06786845,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":93},"biblio":{"volume":null,"issue":null,"first_page":"868","last_page":"873"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.791361927986145},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.7506380677223206},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.6588199734687805},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6508418321609497},{"id":"https://openalex.org/keywords/retiming","display_name":"Retiming","score":0.579729437828064},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.5206241607666016},{"id":"https://openalex.org/keywords/pareto-principle","display_name":"Pareto principle","score":0.5000789165496826},{"id":"https://openalex.org/keywords/register-transfer-level","display_name":"Register-transfer level","score":0.49691370129585266},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.47898340225219727},{"id":"https://openalex.org/keywords/parametric-statistics","display_name":"Parametric statistics","score":0.46596577763557434},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.4643315374851227},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.45547106862068176},{"id":"https://openalex.org/keywords/testability","display_name":"Testability","score":0.4465736746788025},{"id":"https://openalex.org/keywords/multi-objective-optimization","display_name":"Multi-objective optimization","score":0.43623432517051697},{"id":"https://openalex.org/keywords/mathematical-optimization","display_name":"Mathematical optimization","score":0.33616867661476135},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.265779048204422},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.22820773720741272},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.18625473976135254},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.18407398462295532},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.15201684832572937},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.11194673180580139}],"concepts":[{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.791361927986145},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.7506380677223206},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.6588199734687805},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6508418321609497},{"id":"https://openalex.org/C41112130","wikidata":"https://www.wikidata.org/wiki/Q2146175","display_name":"Retiming","level":2,"score":0.579729437828064},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.5206241607666016},{"id":"https://openalex.org/C137635306","wikidata":"https://www.wikidata.org/wiki/Q182667","display_name":"Pareto principle","level":2,"score":0.5000789165496826},{"id":"https://openalex.org/C34854456","wikidata":"https://www.wikidata.org/wiki/Q1484552","display_name":"Register-transfer level","level":4,"score":0.49691370129585266},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.47898340225219727},{"id":"https://openalex.org/C117251300","wikidata":"https://www.wikidata.org/wiki/Q1849855","display_name":"Parametric statistics","level":2,"score":0.46596577763557434},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.4643315374851227},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.45547106862068176},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.4465736746788025},{"id":"https://openalex.org/C68781425","wikidata":"https://www.wikidata.org/wiki/Q2052203","display_name":"Multi-objective optimization","level":2,"score":0.43623432517051697},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.33616867661476135},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.265779048204422},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.22820773720741272},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.18625473976135254},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.18407398462295532},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.15201684832572937},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.11194673180580139},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icacci.2013.6637290","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icacci.2013.6637290","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 International Conference on Advances in Computing, Communications and Informatics (ICACCI)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1964978749","https://openalex.org/W1971829013","https://openalex.org/W1980587820","https://openalex.org/W1984353243","https://openalex.org/W2005582489","https://openalex.org/W2019688018","https://openalex.org/W2067735763","https://openalex.org/W2073429440","https://openalex.org/W2108242004","https://openalex.org/W2113962082","https://openalex.org/W2133537407","https://openalex.org/W2140669431","https://openalex.org/W4242613073","https://openalex.org/W6655294004"],"related_works":["https://openalex.org/W4281926497","https://openalex.org/W2274562545","https://openalex.org/W2269990635","https://openalex.org/W3146054601","https://openalex.org/W2042762783","https://openalex.org/W4283730710","https://openalex.org/W3149594966","https://openalex.org/W4313484792","https://openalex.org/W1905101075","https://openalex.org/W1536721241"],"abstract_inverted_index":{"High":[0],"level":[1,83],"synthesis":[2,84],"(HLS)":[3],"is":[4,35],"the":[5,16,54,59,75],"methodology":[6],"of":[7,33,81],"generating":[8],"Register":[9],"Transfer":[10],"Logic(RTL)":[11],"design":[12,42,87,104,110],"taking":[13],"into":[14],"consideration":[15],"behavioural":[17],"specification":[18],"and":[19,40,71,115,121],"constraints":[20],"within":[21],"an":[22,30,78],"optimized":[23],"cost":[24,70],"function.":[25],"Design":[26],"space":[27,88,105],"exploration":[28,106],"(DSE),":[29],"important":[31],"stage":[32],"HLS,":[34],"a":[36,93,98],"task":[37],"for":[38,47,77,102,119],"identifying":[39],"evaluating":[41],"alternatives":[43],"during":[44],"system":[45],"development":[46],"obtaining":[48],"Pareto":[49,99],"optimal":[50,100],"solution.":[51],"Concerns":[52],"over":[53],"power":[55,120],"dissipation":[56],"coupled":[57],"with":[58,85],"conventional":[60],"metrics":[61],"such":[62],"as":[63],"area,":[64],"time":[65,111],"delay,":[66],"thermal,":[67],"performance,":[68],"reliability,":[69],"testability":[72],"have":[73],"raised":[74],"demand":[76],"efficient":[79],"technique":[80],"high":[82],"better":[86],"exploration.":[89],"This":[90],"paper":[91],"presents":[92],"novel":[94],"approach":[95],"to":[96],"achieve":[97],"solution":[101],"this":[103],"in":[107],"minimum":[108],"possible":[109],"using":[112],"Greedy":[113],"Algorithm":[114],"Priority":[116],"Factor":[117],"(PF)":[118],"timing":[122],"analysis.":[123]},"counts_by_year":[{"year":2021,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}