{"id":"https://openalex.org/W4406416477","doi":"https://doi.org/10.1109/ic3i61595.2024.10828606","title":"Low Power Optimization of Hybrid Logic Full Adder Design using FinFET 32nm Technology","display_name":"Low Power Optimization of Hybrid Logic Full Adder Design using FinFET 32nm Technology","publication_year":2024,"publication_date":"2024-09-18","ids":{"openalex":"https://openalex.org/W4406416477","doi":"https://doi.org/10.1109/ic3i61595.2024.10828606"},"language":"en","primary_location":{"id":"doi:10.1109/ic3i61595.2024.10828606","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ic3i61595.2024.10828606","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 7th International Conference on Contemporary Computing and Informatics (IC3I)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5087530225","display_name":"Sanjeev Kumar","orcid":"https://orcid.org/0000-0002-1783-973X"},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Sanjeev Kumar","raw_affiliation_strings":["Noida Institute of Engineering and Technology,Department of Electronics and Communication Engineering,Greater Noida,Uttar Pradesh,India"],"affiliations":[{"raw_affiliation_string":"Noida Institute of Engineering and Technology,Department of Electronics and Communication Engineering,Greater Noida,Uttar Pradesh,India","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5062150469","display_name":"Kanika Jindal","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Kanika Jindal","raw_affiliation_strings":["Noida Institute of Engineering and Technology,Department of Electronics and Communication Engineering,Greater Noida,Uttar Pradesh,India"],"affiliations":[{"raw_affiliation_string":"Noida Institute of Engineering and Technology,Department of Electronics and Communication Engineering,Greater Noida,Uttar Pradesh,India","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5109708266","display_name":"Pavan K. Shukla","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Pavan Kumar Shukla","raw_affiliation_strings":["Noida Institute of Engineering and Technology,Department of Electronics and Communication Engineering,Greater Noida,Uttar Pradesh,India"],"affiliations":[{"raw_affiliation_string":"Noida Institute of Engineering and Technology,Department of Electronics and Communication Engineering,Greater Noida,Uttar Pradesh,India","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5087530225"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.4449,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.65776334,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":91,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"345","last_page":"349"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9829000234603882,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9800000190734863,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.8056808710098267},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5768762826919556},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4725247025489807},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.44253674149513245},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.4183332324028015},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3626224398612976},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.16655319929122925},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.11563184857368469},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.09432396292686462}],"concepts":[{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.8056808710098267},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5768762826919556},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4725247025489807},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.44253674149513245},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4183332324028015},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3626224398612976},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.16655319929122925},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.11563184857368469},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.09432396292686462},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ic3i61595.2024.10828606","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ic3i61595.2024.10828606","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 7th International Conference on Contemporary Computing and Informatics (IC3I)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.7900000214576721,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2098419840","https://openalex.org/W1966764473","https://openalex.org/W2789349722","https://openalex.org/W1985308002","https://openalex.org/W2056896932","https://openalex.org/W2614722573","https://openalex.org/W2121963733","https://openalex.org/W1977171228","https://openalex.org/W2059422871","https://openalex.org/W2041787842"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,10],"low":[4],"power":[5,31,40,76,94],"optimisation":[6,36,77],"strategy":[7],"for":[8,63,116],"designing":[9],"32nm":[11],"FinFET":[12,50],"hybrid":[13],"logic":[14,27],"full":[15],"adder":[16],"(HLFA).":[17],"The":[18,35],"recommended":[19],"architecture":[20],"uses":[21],"complementary":[22],"metal-oxide-semiconductors":[23],"(CMOS)":[24],"and":[25,33,43,55,85,97],"pass-transistor":[26],"(PTL)":[28],"to":[29,60,70,100],"balance":[30],"consumption":[32],"performance.":[34],"reduces":[37,56],"average":[38,92],"power,":[39,93],"dissipation,":[41,95],"latency,":[42,96],"PDP":[44],"while":[45],"maintaining":[46],"acceptable":[47],"area":[48],"overhead.":[49],"technology":[51,62],"improves":[52],"gate":[53,80],"control":[54],"leakage":[57,86],"currents":[58],"compared":[59],"CMOS":[61],"the":[64,72,101,111],"HLFA.":[65],"HSPICE":[66],"simulation":[67],"is":[68,114],"used":[69],"evaluate":[71],"proposed":[73],"design.":[74],"Low":[75],"solutions":[78],"including":[79],"resizing,":[81],"input":[82],"capacitance":[83],"reduction,":[84],"current":[87],"reduction":[88],"are":[89],"tested":[90],"on":[91],"PDP.":[98],"Due":[99],"research,":[102],"all":[103],"of":[104],"these":[105],"indicators":[106],"have":[107],"improved,":[108],"indicating":[109],"that":[110],"suggested":[112],"design":[113],"suitable":[115],"low-power":[117],"digital":[118],"system":[119],"applications.":[120]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
