{"id":"https://openalex.org/W2184285466","doi":"https://doi.org/10.1109/ic3.2015.7346720","title":"A novel leakage reduction DOIND approach for nanoscale domino logic circuits","display_name":"A novel leakage reduction DOIND approach for nanoscale domino logic circuits","publication_year":2015,"publication_date":"2015-08-01","ids":{"openalex":"https://openalex.org/W2184285466","doi":"https://doi.org/10.1109/ic3.2015.7346720","mag":"2184285466"},"language":"en","primary_location":{"id":"doi:10.1109/ic3.2015.7346720","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ic3.2015.7346720","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 Eighth International Conference on Contemporary Computing (IC3)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5035985978","display_name":"Ambika Prasad Shah","orcid":"https://orcid.org/0000-0003-0810-814X"},"institutions":[{"id":"https://openalex.org/I138272832","display_name":"Devi Ahilya Vishwavidyalaya","ror":"https://ror.org/05c2p1f98","country_code":"IN","type":"education","lineage":["https://openalex.org/I138272832"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Ambika Prasad Shah","raw_affiliation_strings":["Electronics & Telecommunication Engineering Department, IET-Devi Ahilya University, Indore, INDIA"],"affiliations":[{"raw_affiliation_string":"Electronics & Telecommunication Engineering Department, IET-Devi Ahilya University, Indore, INDIA","institution_ids":["https://openalex.org/I138272832"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5063975084","display_name":"Vaibhav Neema","orcid":"https://orcid.org/0000-0003-0922-373X"},"institutions":[{"id":"https://openalex.org/I138272832","display_name":"Devi Ahilya Vishwavidyalaya","ror":"https://ror.org/05c2p1f98","country_code":"IN","type":"education","lineage":["https://openalex.org/I138272832"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Vaibhav Neema","raw_affiliation_strings":["Electronics & Telecommunication Engineering Department, IET-Devi Ahilya University, Indore, INDIA"],"affiliations":[{"raw_affiliation_string":"Electronics & Telecommunication Engineering Department, IET-Devi Ahilya University, Indore, INDIA","institution_ids":["https://openalex.org/I138272832"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5044083563","display_name":"Shreeniwas Daulatabad","orcid":"https://orcid.org/0000-0001-8647-0801"},"institutions":[{"id":"https://openalex.org/I138272832","display_name":"Devi Ahilya Vishwavidyalaya","ror":"https://ror.org/05c2p1f98","country_code":"IN","type":"education","lineage":["https://openalex.org/I138272832"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Shreeniwas Daulatabad","raw_affiliation_strings":["Electronics & Telecommunication Engineering Department, IET-Devi Ahilya University, Indore, INDIA"],"affiliations":[{"raw_affiliation_string":"Electronics & Telecommunication Engineering Department, IET-Devi Ahilya University, Indore, INDIA","institution_ids":["https://openalex.org/I138272832"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5035985978"],"corresponding_institution_ids":["https://openalex.org/I138272832"],"apc_list":null,"apc_paid":null,"fwci":0.3946,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.67490499,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"434","last_page":"438"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/domino-logic","display_name":"Domino logic","score":0.860628604888916},{"id":"https://openalex.org/keywords/noise-margin","display_name":"Noise margin","score":0.6982303857803345},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.6444624662399292},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6294112205505371},{"id":"https://openalex.org/keywords/dynamic-logic","display_name":"Dynamic logic (digital electronics)","score":0.6211994290351868},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.618676483631134},{"id":"https://openalex.org/keywords/power\u2013delay-product","display_name":"Power\u2013delay product","score":0.605618417263031},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5795184373855591},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.5636943578720093},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5498738288879395},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5370959043502808},{"id":"https://openalex.org/keywords/leakage","display_name":"Leakage (economics)","score":0.5224562883377075},{"id":"https://openalex.org/keywords/dynamic-demand","display_name":"Dynamic demand","score":0.5207514762878418},{"id":"https://openalex.org/keywords/domino","display_name":"Domino","score":0.43880656361579895},{"id":"https://openalex.org/keywords/logic-level","display_name":"Logic level","score":0.4352495074272156},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.4349735975265503},{"id":"https://openalex.org/keywords/asynchronous-circuit","display_name":"Asynchronous circuit","score":0.42729657888412476},{"id":"https://openalex.org/keywords/noise-immunity","display_name":"Noise immunity","score":0.42000892758369446},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.3925057649612427},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.36512017250061035},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.3119164705276489},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.3036212921142578},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.25619250535964966},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.25356143712997437},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.21043893694877625},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.10796856880187988},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.10308131575584412},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.083330899477005},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.08298623561859131}],"concepts":[{"id":"https://openalex.org/C2777555262","wikidata":"https://www.wikidata.org/wiki/Q173391","display_name":"Domino logic","level":5,"score":0.860628604888916},{"id":"https://openalex.org/C179499742","wikidata":"https://www.wikidata.org/wiki/Q1324892","display_name":"Noise margin","level":4,"score":0.6982303857803345},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.6444624662399292},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6294112205505371},{"id":"https://openalex.org/C2777796570","wikidata":"https://www.wikidata.org/wiki/Q2351326","display_name":"Dynamic logic (digital electronics)","level":4,"score":0.6211994290351868},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.618676483631134},{"id":"https://openalex.org/C2776391166","wikidata":"https://www.wikidata.org/wiki/Q7236873","display_name":"Power\u2013delay product","level":4,"score":0.605618417263031},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5795184373855591},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.5636943578720093},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5498738288879395},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5370959043502808},{"id":"https://openalex.org/C2777042071","wikidata":"https://www.wikidata.org/wiki/Q6509304","display_name":"Leakage (economics)","level":2,"score":0.5224562883377075},{"id":"https://openalex.org/C45872418","wikidata":"https://www.wikidata.org/wiki/Q5318966","display_name":"Dynamic demand","level":3,"score":0.5207514762878418},{"id":"https://openalex.org/C2776416436","wikidata":"https://www.wikidata.org/wiki/Q3751781","display_name":"Domino","level":3,"score":0.43880656361579895},{"id":"https://openalex.org/C146569638","wikidata":"https://www.wikidata.org/wiki/Q173378","display_name":"Logic level","level":3,"score":0.4352495074272156},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.4349735975265503},{"id":"https://openalex.org/C87695204","wikidata":"https://www.wikidata.org/wiki/Q629971","display_name":"Asynchronous circuit","level":5,"score":0.42729657888412476},{"id":"https://openalex.org/C2988494973","wikidata":"https://www.wikidata.org/wiki/Q179448","display_name":"Noise immunity","level":3,"score":0.42000892758369446},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.3925057649612427},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.36512017250061035},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.3119164705276489},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.3036212921142578},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.25619250535964966},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.25356143712997437},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.21043893694877625},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.10796856880187988},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.10308131575584412},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.083330899477005},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.08298623561859131},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0},{"id":"https://openalex.org/C55493867","wikidata":"https://www.wikidata.org/wiki/Q7094","display_name":"Biochemistry","level":1,"score":0.0},{"id":"https://openalex.org/C161790260","wikidata":"https://www.wikidata.org/wiki/Q82264","display_name":"Catalysis","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ic3.2015.7346720","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ic3.2015.7346720","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 Eighth International Conference on Contemporary Computing (IC3)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8999999761581421}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1521402186","https://openalex.org/W1995713926","https://openalex.org/W2102014077","https://openalex.org/W2104628168","https://openalex.org/W2110620194","https://openalex.org/W2125765139","https://openalex.org/W2157648926","https://openalex.org/W2542641152","https://openalex.org/W6631099819","https://openalex.org/W6676720387"],"related_works":["https://openalex.org/W1513486344","https://openalex.org/W2206334056","https://openalex.org/W2132134751","https://openalex.org/W2553905933","https://openalex.org/W3012469827","https://openalex.org/W2184285466","https://openalex.org/W2587248968","https://openalex.org/W3201227081","https://openalex.org/W2014775954","https://openalex.org/W4312554941"],"abstract_inverted_index":{"Dynamic":[0],"CMOS":[1,27],"logic":[2,31,62,68,89,92],"circuits":[3,9],"are":[4],"used":[5],"in":[6,43,52],"modern":[7],"VLSI":[8],"because":[10],"of":[11,55],"its":[12,17],"high":[13,20],"system":[14],"performance":[15,18,53],"and":[16,37,90,113,134],"is":[19,64,79],"due":[21],"to":[22],"higher":[23],"speed":[24],"over":[25],"static":[26,110,114],"circuit.":[28],"However":[29],"dynamic":[30,56,125,128,135],"circuit":[32,122],"has":[33],"less":[34],"noise":[35,49],"immunity":[36],"increased":[38],"leakage":[39,44,72,107],"power":[40,111,126,136],"dissipation.":[41],"Increase":[42],"current":[45,73,108],"combine":[46],"with":[47,74],"reduced":[48],"margin":[50],"results":[51,99],"degradation":[54],"circuits.":[57],"In":[58],"this":[59],"paper":[60],"DOIND":[61,91,103],"approach":[63,104],"proposed":[65,102],"for":[66,86],"domino":[67,88],"which":[69],"reduces":[70],"the":[71,106],"minimum":[75],"delay":[76,130,137],"penalty.":[77],"Simulation":[78,98],"performed":[80],"at":[81,117,141],"70":[82],"nm":[83],"technology":[84],"node":[85],"a":[87],"buffer":[93],"using":[94],"tanner":[95],"EDA":[96],"tool.":[97],"shows":[100],"that":[101],"decreases":[105],"93.3%,":[109],"93.3%":[112],"energy":[115,129],"86.66%":[116],"supply":[118,143],"voltage":[119],"1.15V.":[120],"Proposed":[121],"also":[123],"improves":[124],"60.78%,":[127],"product":[131,138],"(EDP)":[132],"62.18%":[133],"(PDP)":[139],"62.07%":[140],"1.15V":[142],"voltage.":[144]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2016,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
