{"id":"https://openalex.org/W1565757145","doi":"https://doi.org/10.1109/i2mtc.2015.7151514","title":"Direct FPGA-based power profiling for a RISC processor","display_name":"Direct FPGA-based power profiling for a RISC processor","publication_year":2015,"publication_date":"2015-05-01","ids":{"openalex":"https://openalex.org/W1565757145","doi":"https://doi.org/10.1109/i2mtc.2015.7151514","mag":"1565757145"},"language":"en","primary_location":{"id":"doi:10.1109/i2mtc.2015.7151514","is_oa":false,"landing_page_url":"https://doi.org/10.1109/i2mtc.2015.7151514","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE International Instrumentation and Measurement Technology Conference (I2MTC) Proceedings","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5000354498","display_name":"Cosmin Cern\u0103zanu-Gl\u0103van","orcid":"https://orcid.org/0000-0002-2221-0776"},"institutions":[{"id":"https://openalex.org/I3122695212","display_name":"Polytechnic University of Timi\u015foara","ror":"https://ror.org/02v91gy68","country_code":"RO","type":"education","lineage":["https://openalex.org/I3122695212"]}],"countries":["RO"],"is_corresponding":true,"raw_author_name":"Cosmin Cernazanu-Glavan","raw_affiliation_strings":["Universitatea Politehnica din Timisoara, Timisoara, RO"],"affiliations":[{"raw_affiliation_string":"Universitatea Politehnica din Timisoara, Timisoara, RO","institution_ids":["https://openalex.org/I3122695212"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5079716965","display_name":"Marius Marcu","orcid":"https://orcid.org/0000-0003-3394-385X"},"institutions":[{"id":"https://openalex.org/I3122695212","display_name":"Polytechnic University of Timi\u015foara","ror":"https://ror.org/02v91gy68","country_code":"RO","type":"education","lineage":["https://openalex.org/I3122695212"]}],"countries":["RO"],"is_corresponding":false,"raw_author_name":"Marius Marcu","raw_affiliation_strings":["Computer and Software Engineering Politehnica, University of Timisoara, Romania"],"affiliations":[{"raw_affiliation_string":"Computer and Software Engineering Politehnica, University of Timisoara, Romania","institution_ids":["https://openalex.org/I3122695212"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5045308058","display_name":"Alexandru Amaric\u0103i","orcid":"https://orcid.org/0000-0002-2706-1781"},"institutions":[{"id":"https://openalex.org/I3122695212","display_name":"Polytechnic University of Timi\u015foara","ror":"https://ror.org/02v91gy68","country_code":"RO","type":"education","lineage":["https://openalex.org/I3122695212"]}],"countries":["RO"],"is_corresponding":false,"raw_author_name":"Alexandru Amaricai","raw_affiliation_strings":["Computer and Software Engineering Politehnica, University of Timisoara, Romania"],"affiliations":[{"raw_affiliation_string":"Computer and Software Engineering Politehnica, University of Timisoara, Romania","institution_ids":["https://openalex.org/I3122695212"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5013044047","display_name":"Stefan Fedeac","orcid":null},"institutions":[{"id":"https://openalex.org/I3122695212","display_name":"Polytechnic University of Timi\u015foara","ror":"https://ror.org/02v91gy68","country_code":"RO","type":"education","lineage":["https://openalex.org/I3122695212"]}],"countries":["RO"],"is_corresponding":false,"raw_author_name":"Stefan Fedeac","raw_affiliation_strings":["Computer and Software Engineering Politehnica, University of Timisoara, Romania"],"affiliations":[{"raw_affiliation_string":"Computer and Software Engineering Politehnica, University of Timisoara, Romania","institution_ids":["https://openalex.org/I3122695212"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5043723347","display_name":"Madalin Ghenea","orcid":null},"institutions":[{"id":"https://openalex.org/I3122695212","display_name":"Polytechnic University of Timi\u015foara","ror":"https://ror.org/02v91gy68","country_code":"RO","type":"education","lineage":["https://openalex.org/I3122695212"]}],"countries":["RO"],"is_corresponding":false,"raw_author_name":"Madalin Ghenea","raw_affiliation_strings":["Computer and Software Engineering Politehnica, University of Timisoara, Romania"],"affiliations":[{"raw_affiliation_string":"Computer and Software Engineering Politehnica, University of Timisoara, Romania","institution_ids":["https://openalex.org/I3122695212"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100401045","display_name":"Zheng Wang","orcid":"https://orcid.org/0000-0001-6157-0662"},"institutions":[{"id":"https://openalex.org/I887968799","display_name":"RWTH Aachen University","ror":"https://ror.org/04xfq0f34","country_code":"DE","type":"education","lineage":["https://openalex.org/I887968799"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Zheng Wang","raw_affiliation_strings":["MPSoC Architecture Research Group, RWTH-Aachen University, Aachen, Germany"],"affiliations":[{"raw_affiliation_string":"MPSoC Architecture Research Group, RWTH-Aachen University, Aachen, Germany","institution_ids":["https://openalex.org/I887968799"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5089860351","display_name":"Anupam Chattopadhyay","orcid":"https://orcid.org/0000-0002-8818-6983"},"institutions":[{"id":"https://openalex.org/I887968799","display_name":"RWTH Aachen University","ror":"https://ror.org/04xfq0f34","country_code":"DE","type":"education","lineage":["https://openalex.org/I887968799"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Anupam Chattopadhyay","raw_affiliation_strings":["MPSoC Architecture Research Group, RWTH-Aachen University, Aachen, Germany"],"affiliations":[{"raw_affiliation_string":"MPSoC Architecture Research Group, RWTH-Aachen University, Aachen, Germany","institution_ids":["https://openalex.org/I887968799"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5081081586","display_name":"Jan Henrik Weinstock","orcid":"https://orcid.org/0009-0008-0902-7652"},"institutions":[{"id":"https://openalex.org/I887968799","display_name":"RWTH Aachen University","ror":"https://ror.org/04xfq0f34","country_code":"DE","type":"education","lineage":["https://openalex.org/I887968799"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Jan Weinstock","raw_affiliation_strings":["MPSoC Architecture Research Group, RWTH-Aachen University, Aachen, Germany"],"affiliations":[{"raw_affiliation_string":"MPSoC Architecture Research Group, RWTH-Aachen University, Aachen, Germany","institution_ids":["https://openalex.org/I887968799"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5023470562","display_name":"Rainer Leupers","orcid":"https://orcid.org/0000-0002-6735-3033"},"institutions":[{"id":"https://openalex.org/I887968799","display_name":"RWTH Aachen University","ror":"https://ror.org/04xfq0f34","country_code":"DE","type":"education","lineage":["https://openalex.org/I887968799"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Rainer Leupers","raw_affiliation_strings":["MPSoC Architecture Research Group, RWTH-Aachen University, Aachen, Germany"],"affiliations":[{"raw_affiliation_string":"MPSoC Architecture Research Group, RWTH-Aachen University, Aachen, Germany","institution_ids":["https://openalex.org/I887968799"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":9,"corresponding_author_ids":["https://openalex.org/A5000354498"],"corresponding_institution_ids":["https://openalex.org/I3122695212"],"apc_list":null,"apc_paid":null,"fwci":0.3299,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.57713296,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":"44","issue":null,"first_page":"1578","last_page":"1583"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8083603382110596},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7783085107803345},{"id":"https://openalex.org/keywords/reduced-instruction-set-computing","display_name":"Reduced instruction set computing","score":0.732492983341217},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.6680361032485962},{"id":"https://openalex.org/keywords/fpga-prototype","display_name":"FPGA prototype","score":0.6380727291107178},{"id":"https://openalex.org/keywords/profiling","display_name":"Profiling (computer programming)","score":0.6137634515762329},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5953992605209351},{"id":"https://openalex.org/keywords/application-specific-instruction-set-processor","display_name":"Application-specific instruction-set processor","score":0.5206260085105896},{"id":"https://openalex.org/keywords/spec#","display_name":"Spec#","score":0.44554603099823},{"id":"https://openalex.org/keywords/power-analysis","display_name":"Power analysis","score":0.43923261761665344},{"id":"https://openalex.org/keywords/dynamic-demand","display_name":"Dynamic demand","score":0.436741441488266},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.4231293201446533},{"id":"https://openalex.org/keywords/processor-design","display_name":"Processor design","score":0.42264634370803833},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.38944652676582336},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3534306287765503},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.34101754426956177},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3280165195465088},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.11793312430381775},{"id":"https://openalex.org/keywords/cryptography","display_name":"Cryptography","score":0.09255984425544739}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8083603382110596},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7783085107803345},{"id":"https://openalex.org/C126298526","wikidata":"https://www.wikidata.org/wiki/Q189376","display_name":"Reduced instruction set computing","level":3,"score":0.732492983341217},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.6680361032485962},{"id":"https://openalex.org/C203864433","wikidata":"https://www.wikidata.org/wiki/Q5426992","display_name":"FPGA prototype","level":3,"score":0.6380727291107178},{"id":"https://openalex.org/C187191949","wikidata":"https://www.wikidata.org/wiki/Q1138496","display_name":"Profiling (computer programming)","level":2,"score":0.6137634515762329},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5953992605209351},{"id":"https://openalex.org/C201736964","wikidata":"https://www.wikidata.org/wiki/Q621583","display_name":"Application-specific instruction-set processor","level":3,"score":0.5206260085105896},{"id":"https://openalex.org/C2778565505","wikidata":"https://www.wikidata.org/wiki/Q2207566","display_name":"Spec#","level":2,"score":0.44554603099823},{"id":"https://openalex.org/C71743495","wikidata":"https://www.wikidata.org/wiki/Q2845210","display_name":"Power analysis","level":3,"score":0.43923261761665344},{"id":"https://openalex.org/C45872418","wikidata":"https://www.wikidata.org/wiki/Q5318966","display_name":"Dynamic demand","level":3,"score":0.436741441488266},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.4231293201446533},{"id":"https://openalex.org/C526435321","wikidata":"https://www.wikidata.org/wiki/Q1303814","display_name":"Processor design","level":2,"score":0.42264634370803833},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.38944652676582336},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3534306287765503},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.34101754426956177},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3280165195465088},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.11793312430381775},{"id":"https://openalex.org/C178489894","wikidata":"https://www.wikidata.org/wiki/Q8789","display_name":"Cryptography","level":2,"score":0.09255984425544739},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/i2mtc.2015.7151514","is_oa":false,"landing_page_url":"https://doi.org/10.1109/i2mtc.2015.7151514","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE International Instrumentation and Measurement Technology Conference (I2MTC) Proceedings","raw_type":"proceedings-article"},{"id":"pmh:oai:publications.rwth-aachen.de:564349","is_oa":false,"landing_page_url":"https://publications.rwth-aachen.de/record/564349","pdf_url":null,"source":{"id":"https://openalex.org/S4306401362","display_name":"RWTH Publications (RWTH Aachen)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I887968799","host_organization_name":"RWTH Aachen University","host_organization_lineage":["https://openalex.org/I887968799"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"2015 IEEE International Instrumentation and Measurement Technology Conference (I2MTC) : 11 - 14 May 2015, Pisa, Italy / organized and sponsored by: IEEE, IEEE Instrumentation  Measurement Society. Ed. Alessandro Ferrero ... - Vol. 3<br/>2015 IEEE International Instrumentation and Measurement Technology Conference (I2MTC), I2MTC, Pisa, Italy, 2015-05-11 - 2015-05-14","raw_type":"info:eu-repo/semantics/publishedVersion"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8999999761581421,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1573455007","https://openalex.org/W1964564580","https://openalex.org/W1977850862","https://openalex.org/W2008549213","https://openalex.org/W2042678339","https://openalex.org/W2106230392","https://openalex.org/W2113604805","https://openalex.org/W2125999955","https://openalex.org/W2135533400","https://openalex.org/W2185943396","https://openalex.org/W2540350541","https://openalex.org/W2615865818","https://openalex.org/W2985821113"],"related_works":["https://openalex.org/W2900306051","https://openalex.org/W2036206036","https://openalex.org/W4387540511","https://openalex.org/W182515070","https://openalex.org/W2993622674","https://openalex.org/W4367172762","https://openalex.org/W4309639889","https://openalex.org/W4280644180","https://openalex.org/W4388344772","https://openalex.org/W3116750762"],"abstract_inverted_index":{"This":[0],"paper":[1],"investigates":[2],"the":[3,17,30,43,53,79,82,112],"possibility":[4],"of":[5,10,56,75,81,88],"creating":[6],"an":[7],"energy":[8],"profile":[9],"a":[11,89],"RISC":[12,90],"processor":[13,44,91],"instruction":[14],"set":[15],"in":[16,94],"prototyping":[18],"phase,":[19],"using":[20],"FPGA":[21,113],"implementation":[22,45],"and":[23,40,59,69,100,118],"physical":[24,115],"measurements.":[25],"In":[26],"order":[27],"to":[28],"determine":[29],"power":[31,86,104,116,121],"consumption":[32,87],"at":[33,52],"instruction-level,":[34],"several":[35],"programs":[36],"have":[37,50],"been":[38],"developed":[39],"run":[41],"on":[42,46],"FPGA.":[47],"The":[48,72,107],"experiments":[49],"focused":[51],"following":[54],"groups":[55],"instructions:":[57],"arithmetic":[58],"logic":[60],"(ALU)":[61],"instructions,":[62,65,67],"memory":[63],"access":[64],"control":[66],"compare":[68],"move":[70],"instructions.":[71],"main":[73],"goal":[74],"our":[76],"work":[77],"is":[78,123],"investigation":[80],"correlation":[83,109],"between":[84,111],"dynamic":[85],"design":[92],"implemented":[93],"different":[95],"technologies":[96],"(FPGA":[97],"vs.":[98],"ASIC)":[99],"manufacturing":[101],"processes,":[102],"called":[103],"technology":[105],"gap.":[106],"achieved":[108],"coefficient":[110],"45nm":[114,120],"measurements":[117],"ASIC":[119],"estimation":[122],"86.39%.":[124]},"counts_by_year":[{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":3},{"year":2019,"cited_by_count":1},{"year":2015,"cited_by_count":1}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}
