{"id":"https://openalex.org/W2081567565","doi":"https://doi.org/10.1109/i2mtc.2014.6861000","title":"Analysis and implementation of low-cost FPGA-based digital pulse-width modulators","display_name":"Analysis and implementation of low-cost FPGA-based digital pulse-width modulators","publication_year":2014,"publication_date":"2014-05-01","ids":{"openalex":"https://openalex.org/W2081567565","doi":"https://doi.org/10.1109/i2mtc.2014.6861000","mag":"2081567565"},"language":"en","primary_location":{"id":"doi:10.1109/i2mtc.2014.6861000","is_oa":false,"landing_page_url":"https://doi.org/10.1109/i2mtc.2014.6861000","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 IEEE International Instrumentation and Measurement Technology Conference (I2MTC) Proceedings","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5050895346","display_name":"Ignacio De Le\u00f3n","orcid":null},"institutions":[{"id":"https://openalex.org/I180910786","display_name":"Universidad de la Rep\u00fablica","ror":"https://ror.org/030bbe882","country_code":"UY","type":"education","lineage":["https://openalex.org/I180910786"]}],"countries":["UY"],"is_corresponding":true,"raw_author_name":"Ignacio de Leon","raw_affiliation_strings":["Universidad de la Republica Uruguay, Montevideo, Montevideo, UY"],"affiliations":[{"raw_affiliation_string":"Universidad de la Republica Uruguay, Montevideo, Montevideo, UY","institution_ids":["https://openalex.org/I180910786"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5001128293","display_name":"Gonzalo Sotta","orcid":null},"institutions":[{"id":"https://openalex.org/I180910786","display_name":"Universidad de la Rep\u00fablica","ror":"https://ror.org/030bbe882","country_code":"UY","type":"education","lineage":["https://openalex.org/I180910786"]}],"countries":["UY"],"is_corresponding":false,"raw_author_name":"Gonzalo Sotta","raw_affiliation_strings":["Universidad de la Republica Uruguay, Montevideo, Montevideo, UY"],"affiliations":[{"raw_affiliation_string":"Universidad de la Republica Uruguay, Montevideo, Montevideo, UY","institution_ids":["https://openalex.org/I180910786"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5072752588","display_name":"Gabriel Eirea","orcid":null},"institutions":[{"id":"https://openalex.org/I180910786","display_name":"Universidad de la Rep\u00fablica","ror":"https://ror.org/030bbe882","country_code":"UY","type":"education","lineage":["https://openalex.org/I180910786"]}],"countries":["UY"],"is_corresponding":false,"raw_author_name":"Gabriel Eirea","raw_affiliation_strings":["Universidad de la Republica Uruguay, Montevideo, Montevideo, UY"],"affiliations":[{"raw_affiliation_string":"Universidad de la Republica Uruguay, Montevideo, Montevideo, UY","institution_ids":["https://openalex.org/I180910786"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5077786972","display_name":"Julio P\u00e9rez Acle","orcid":"https://orcid.org/0000-0001-9259-558X"},"institutions":[{"id":"https://openalex.org/I180910786","display_name":"Universidad de la Rep\u00fablica","ror":"https://ror.org/030bbe882","country_code":"UY","type":"education","lineage":["https://openalex.org/I180910786"]}],"countries":["UY"],"is_corresponding":false,"raw_author_name":"Julio Perez Acle","raw_affiliation_strings":["Universidad de la Republica Uruguay, Montevideo, Montevideo, UY"],"affiliations":[{"raw_affiliation_string":"Universidad de la Republica Uruguay, Montevideo, Montevideo, UY","institution_ids":["https://openalex.org/I180910786"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5050895346"],"corresponding_institution_ids":["https://openalex.org/I180910786"],"apc_list":null,"apc_paid":null,"fwci":0.5771,"has_fulltext":false,"cited_by_count":10,"citation_normalized_percentile":{"value":0.69671009,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1523","last_page":"1528"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10175","display_name":"Advanced DC-DC Converters","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/serdes","display_name":"SerDes","score":0.8760210871696472},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6993240118026733},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6668746471405029},{"id":"https://openalex.org/keywords/serialization","display_name":"Serialization","score":0.5904644131660461},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.5163951516151428},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.48620787262916565},{"id":"https://openalex.org/keywords/duty-cycle","display_name":"Duty cycle","score":0.4732675552368164},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.47103172540664673},{"id":"https://openalex.org/keywords/serial-communication","display_name":"Serial communication","score":0.4706123471260071},{"id":"https://openalex.org/keywords/synchronization","display_name":"Synchronization (alternating current)","score":0.4268084466457367},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4223380386829376},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3407025933265686},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.19443351030349731},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1928112506866455},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1594579517841339},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.13254481554031372},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.10201910138130188}],"concepts":[{"id":"https://openalex.org/C19707634","wikidata":"https://www.wikidata.org/wiki/Q6510662","display_name":"SerDes","level":2,"score":0.8760210871696472},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6993240118026733},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6668746471405029},{"id":"https://openalex.org/C52723943","wikidata":"https://www.wikidata.org/wiki/Q1127410","display_name":"Serialization","level":2,"score":0.5904644131660461},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.5163951516151428},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.48620787262916565},{"id":"https://openalex.org/C199822604","wikidata":"https://www.wikidata.org/wiki/Q557120","display_name":"Duty cycle","level":3,"score":0.4732675552368164},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.47103172540664673},{"id":"https://openalex.org/C51707140","wikidata":"https://www.wikidata.org/wiki/Q518280","display_name":"Serial communication","level":2,"score":0.4706123471260071},{"id":"https://openalex.org/C2778562939","wikidata":"https://www.wikidata.org/wiki/Q1298791","display_name":"Synchronization (alternating current)","level":3,"score":0.4268084466457367},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4223380386829376},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3407025933265686},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.19443351030349731},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1928112506866455},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1594579517841339},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.13254481554031372},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.10201910138130188},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/i2mtc.2014.6861000","is_oa":false,"landing_page_url":"https://doi.org/10.1109/i2mtc.2014.6861000","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 IEEE International Instrumentation and Measurement Technology Conference (I2MTC) Proceedings","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.716.4974","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.716.4974","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://iie.fing.edu.uy/%7Egeirea/pub/i2mtc2014.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W587567931","https://openalex.org/W2015784750","https://openalex.org/W2097736525","https://openalex.org/W2102330273","https://openalex.org/W2103553287","https://openalex.org/W2131296371","https://openalex.org/W2135731882","https://openalex.org/W2153302213"],"related_works":["https://openalex.org/W2059211473","https://openalex.org/W2370946677","https://openalex.org/W2157372760","https://openalex.org/W2360313402","https://openalex.org/W2468978622","https://openalex.org/W2734937843","https://openalex.org/W2351571607","https://openalex.org/W2728034738","https://openalex.org/W2547446622","https://openalex.org/W2757255852"],"abstract_inverted_index":{"This":[0,131],"paper":[1],"describes":[2],"the":[3,31,38,51,65,69,82,86,101,106,109,125,129,190],"architecture":[4,58,111,180],"and":[5,77,149,173],"operating":[6],"principles":[7],"of":[8,37,91,124,128],"two":[9],"digital":[10],"pulse-width":[11],"modulator":[12],"(DPWM)":[13],"implementations":[14],"for":[15,137,160],"low-cost":[16,166],"field-programmable":[17],"gate":[18],"arrays":[19],"(FPGAs).":[20],"Both":[21],"architectures":[22,162],"are":[23,94,158],"based":[24],"on":[25,140,164,189],"a":[26,78,113,121,182,194],"counter-comparator":[27],"block":[28],"to":[29,45,50,73,80,96,119,176],"process":[30],"most":[32],"significant":[33,53],"bits":[34,54],"(MSB)":[35],"portion":[36,127],"reference":[39],"input,":[40],"enriched":[41],"with":[42,85],"additional":[43],"elements":[44],"enhance":[46],"duty-cycle":[47],"resolution":[48],"according":[49],"less":[52],"(LSB).":[55],"The":[56,178,186],"first":[57,179],"described":[59],"has":[60],"already":[61],"been":[62],"reported":[63],"in":[64],"literature,":[66],"it":[67,200],"uses":[68],"on-chip":[70],"PLL":[71,92],"blocks":[72],"generate":[74],"fixed":[75],"delays":[76,93],"selector":[79],"choose":[81],"one":[83],"corresponding":[84],"desired":[87],"duty-cycle.":[88],"Post-fitting":[89],"adjustments":[90],"required":[95],"compensate":[97],"delay":[98,204],"differences":[99],"between":[100],"diverse":[102],"signal":[103],"paths":[104],"across":[105],"selector.":[107],"In":[108],"second":[110,187],"described,":[112],"serializer-deserializer":[114],"(SERDES)":[115],"module":[116],"is":[117,134,150,193],"used":[118,136],"serialize":[120],"thermometer-coded":[122],"representation":[123],"LSB":[126],"input.":[130],"serialization":[132],"technique":[133],"commonly":[135],"data":[138,144],"transmission":[139,145],"high-speed":[141],"serial":[142],"I/O":[143],"standards":[146],"like":[147],"LVDS":[148],"extensively":[151],"supported":[152],"by":[153],"FPGA":[154,167],"providers.":[155],"Experimental":[156],"results":[157],"presented":[159],"both":[161],"synthesized":[163],"standard":[165],"chips,":[168],"showing":[169],"very":[170],"good":[171],"linearity":[172],"resolutions":[174],"up":[175],"1ns.":[177],"provides":[181],"moderately":[183],"better":[184],"resolution.":[185],"architecture,":[188],"other":[191],"hand,":[192],"much":[195],"more":[196],"robust":[197],"solution":[198],"as":[199],"requires":[201],"no":[202],"post-fitting":[203],"adjustments.":[205]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":1}],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}
