{"id":"https://openalex.org/W2426572037","doi":"https://doi.org/10.1109/hst.2016.7495587","title":"A secure camouflaged threshold voltage defined logic family","display_name":"A secure camouflaged threshold voltage defined logic family","publication_year":2016,"publication_date":"2016-05-01","ids":{"openalex":"https://openalex.org/W2426572037","doi":"https://doi.org/10.1109/hst.2016.7495587","mag":"2426572037"},"language":"en","primary_location":{"id":"doi:10.1109/hst.2016.7495587","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hst.2016.7495587","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5084133129","display_name":"Burak Erbagci","orcid":null},"institutions":[{"id":"https://openalex.org/I74973139","display_name":"Carnegie Mellon University","ror":"https://ror.org/05x2bcf33","country_code":"US","type":"education","lineage":["https://openalex.org/I74973139"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Burak Erbagci","raw_affiliation_strings":["Electrical and Computer Engineering Department, Carnegie Mellon University, Pittsburgh, PA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering Department, Carnegie Mellon University, Pittsburgh, PA, USA","institution_ids":["https://openalex.org/I74973139"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5046962307","display_name":"Cagri Erbagci","orcid":null},"institutions":[{"id":"https://openalex.org/I74973139","display_name":"Carnegie Mellon University","ror":"https://ror.org/05x2bcf33","country_code":"US","type":"education","lineage":["https://openalex.org/I74973139"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Cagri Erbagci","raw_affiliation_strings":["Electrical and Computer Engineering Department, Carnegie Mellon University, Pittsburgh, PA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering Department, Carnegie Mellon University, Pittsburgh, PA, USA","institution_ids":["https://openalex.org/I74973139"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5034758487","display_name":"Nail Etkin Can Akkaya","orcid":null},"institutions":[{"id":"https://openalex.org/I74973139","display_name":"Carnegie Mellon University","ror":"https://ror.org/05x2bcf33","country_code":"US","type":"education","lineage":["https://openalex.org/I74973139"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Nail Etkin Can Akkaya","raw_affiliation_strings":["Electrical and Computer Engineering Department, Carnegie Mellon University, Pittsburgh, PA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering Department, Carnegie Mellon University, Pittsburgh, PA, USA","institution_ids":["https://openalex.org/I74973139"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5000377660","display_name":"Ken Mai","orcid":"https://orcid.org/0000-0002-9096-8757"},"institutions":[{"id":"https://openalex.org/I74973139","display_name":"Carnegie Mellon University","ror":"https://ror.org/05x2bcf33","country_code":"US","type":"education","lineage":["https://openalex.org/I74973139"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ken Mai","raw_affiliation_strings":["Electrical and Computer Engineering Department, Carnegie Mellon University, Pittsburgh, PA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering Department, Carnegie Mellon University, Pittsburgh, PA, USA","institution_ids":["https://openalex.org/I74973139"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":6.7296,"has_fulltext":false,"cited_by_count":62,"citation_normalized_percentile":{"value":0.97242948,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"229","last_page":"235"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9939000010490417,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11601","display_name":"Neuroscience and Neural Engineering","score":0.9585999846458435,"subfield":{"id":"https://openalex.org/subfields/2804","display_name":"Cellular and Molecular Neuroscience"},"field":{"id":"https://openalex.org/fields/28","display_name":"Neuroscience"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.6721534729003906},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6660930514335632},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.6377257704734802},{"id":"https://openalex.org/keywords/logic-block","display_name":"Logic block","score":0.5903334617614746},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5652406215667725},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.5589621067047119},{"id":"https://openalex.org/keywords/robustness","display_name":"Robustness (evolution)","score":0.493326336145401},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.47476935386657715},{"id":"https://openalex.org/keywords/or-gate","display_name":"OR gate","score":0.43355071544647217},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.43317437171936035},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4329535961151123},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4267725348472595},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4147493243217468},{"id":"https://openalex.org/keywords/and-or-invert","display_name":"AND-OR-Invert","score":0.414402574300766},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.38235628604888916},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.3551037311553955},{"id":"https://openalex.org/keywords/and-gate","display_name":"AND gate","score":0.3138285279273987},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.31327080726623535},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.23766165971755981},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.23335161805152893},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2166043221950531},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.18985649943351746}],"concepts":[{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.6721534729003906},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6660930514335632},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.6377257704734802},{"id":"https://openalex.org/C2778325283","wikidata":"https://www.wikidata.org/wiki/Q1125244","display_name":"Logic block","level":3,"score":0.5903334617614746},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5652406215667725},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.5589621067047119},{"id":"https://openalex.org/C63479239","wikidata":"https://www.wikidata.org/wiki/Q7353546","display_name":"Robustness (evolution)","level":3,"score":0.493326336145401},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.47476935386657715},{"id":"https://openalex.org/C58140894","wikidata":"https://www.wikidata.org/wiki/Q560398","display_name":"OR gate","level":4,"score":0.43355071544647217},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.43317437171936035},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4329535961151123},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4267725348472595},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4147493243217468},{"id":"https://openalex.org/C130126468","wikidata":"https://www.wikidata.org/wiki/Q4652943","display_name":"AND-OR-Invert","level":5,"score":0.414402574300766},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.38235628604888916},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.3551037311553955},{"id":"https://openalex.org/C10418432","wikidata":"https://www.wikidata.org/wiki/Q560370","display_name":"AND gate","level":3,"score":0.3138285279273987},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.31327080726623535},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.23766165971755981},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.23335161805152893},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2166043221950531},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.18985649943351746},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0},{"id":"https://openalex.org/C55493867","wikidata":"https://www.wikidata.org/wiki/Q7094","display_name":"Biochemistry","level":1,"score":0.0},{"id":"https://openalex.org/C104317684","wikidata":"https://www.wikidata.org/wiki/Q7187","display_name":"Gene","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/hst.2016.7495587","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hst.2016.7495587","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":39,"referenced_works":["https://openalex.org/W282964191","https://openalex.org/W1485817150","https://openalex.org/W1505879652","https://openalex.org/W1524250393","https://openalex.org/W1537457782","https://openalex.org/W1549320745","https://openalex.org/W1602420333","https://openalex.org/W1613874182","https://openalex.org/W1655262183","https://openalex.org/W1970852936","https://openalex.org/W1998894479","https://openalex.org/W2029979276","https://openalex.org/W2030869830","https://openalex.org/W2032804309","https://openalex.org/W2045818632","https://openalex.org/W2046206102","https://openalex.org/W2048547443","https://openalex.org/W2052353102","https://openalex.org/W2063615695","https://openalex.org/W2067276029","https://openalex.org/W2100734746","https://openalex.org/W2106409910","https://openalex.org/W2112173236","https://openalex.org/W2114864411","https://openalex.org/W2124954128","https://openalex.org/W2135211381","https://openalex.org/W2140904634","https://openalex.org/W2151634003","https://openalex.org/W2154909745","https://openalex.org/W2161998562","https://openalex.org/W2166778460","https://openalex.org/W2171466005","https://openalex.org/W4231363479","https://openalex.org/W4234154886","https://openalex.org/W4285719527","https://openalex.org/W6636388380","https://openalex.org/W6675797392","https://openalex.org/W6681768057","https://openalex.org/W6682554491"],"related_works":["https://openalex.org/W1017999001","https://openalex.org/W2765195743","https://openalex.org/W1979361505","https://openalex.org/W4212898802","https://openalex.org/W2024713617","https://openalex.org/W1593362825","https://openalex.org/W2060067973","https://openalex.org/W2118713399","https://openalex.org/W4287590888","https://openalex.org/W2616524835"],"abstract_inverted_index":{"A":[0],"myriad":[1],"of":[2,12,22,34,82,183,211],"security":[3,167,207],"vulnerabilites":[4],"can":[5,53],"be":[6,198],"exposed":[7],"via":[8,37],"the":[9,13,29,35,60,80,93,110,148,172],"reverse":[10,24],"engineering":[11,25],"integrated":[14],"circuits":[15],"contained":[16],"in":[17,135],"electronics":[18],"systems.":[19],"The":[20],"goal":[21],"IC":[23],"is":[26,115],"to":[27,91,197,205],"uncover":[28],"functionality":[30],"and":[31,45,67,114,130,164,188,204],"internal":[32],"structure":[33,113],"chip":[36],"techniques":[38],"such":[39],"as":[40],"depackaging/delayering,":[41],"high-resolution":[42],"imaging,":[43],"probing,":[44],"side-channel":[46],"examination.":[47],"With":[48],"this":[49],"knowledge,":[50],"an":[51,136],"attacker":[52],"more":[54],"efficiently":[55],"mount":[56],"various":[57,166,181,209],"attacks,":[58],"clone/-counterfeit":[59],"design":[61,129],"possibly":[62],"with":[63,88,120],"hardware":[64],"Trojans":[65],"inserted,":[66],"discover":[68],"trade":[69],"secrets.":[70],"We":[71,128],"propose":[72],"a":[73],"gate":[74,95,108,185],"camouflaging":[75,103],"technique":[76],"that":[77],"relies":[78],"on":[79],"usage":[81],"different":[83,121,125],"threshold":[84,99,122],"voltage":[85,100],"transistors,":[86],"but":[87],"identical":[89],"layouts,":[90],"determine":[92],"logic":[94,107,133,149,193],"function.":[96],"In":[97],"our":[98],"defined":[101],"(TVD)":[102],"technique,":[104],"every":[105],"TVD":[106,132,184,192],"has":[109],"same":[111],"physical":[112],"one":[116],"time":[117],"mask":[118],"programmed":[119],"implants":[123],"for":[124,151,160,165,176],"boolean":[126],"functionality.":[127],"implement":[131],"gates":[134,194],"industrial":[137],"65nm":[138],"bulk":[139],"CMOS":[140,199],"process.":[141],"Using":[142],"post-layout":[143],"extracted":[144],"simulation,":[145],"we":[146,170],"evaluate":[147,171],"style":[150],"VLSI":[152],"overheads":[153,175],"(area,":[154],"power,":[155],"delay)":[156],"versus":[157],"conventional":[158],"logic,":[159],"process":[161,200],"variablity":[162],"robustness,":[163],"metrics.":[168],"Further,":[169],"macro":[173],"block":[174],"ISCAS":[177],"benchmark":[178],"designs":[179],"under":[180],"levels":[182],"replacement":[186],"upto":[187],"including":[189],"100%":[190],"replacement.":[191],"are":[195],"found":[196],"compatible,":[201],"low":[202],"overhead,":[203],"increase":[206],"against":[208],"forms":[210],"attacks.":[212]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":4},{"year":2024,"cited_by_count":4},{"year":2023,"cited_by_count":9},{"year":2022,"cited_by_count":3},{"year":2021,"cited_by_count":8},{"year":2020,"cited_by_count":11},{"year":2019,"cited_by_count":6},{"year":2018,"cited_by_count":8},{"year":2017,"cited_by_count":6},{"year":2016,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}