{"id":"https://openalex.org/W1987134536","doi":"https://doi.org/10.1109/hst.2012.6224315","title":"SDMLp: On the use of complementary Pass transistor Logic for design of DPA resistant circuits","display_name":"SDMLp: On the use of complementary Pass transistor Logic for design of DPA resistant circuits","publication_year":2012,"publication_date":"2012-06-01","ids":{"openalex":"https://openalex.org/W1987134536","doi":"https://doi.org/10.1109/hst.2012.6224315","mag":"1987134536"},"language":"en","primary_location":{"id":"doi:10.1109/hst.2012.6224315","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hst.2012.6224315","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE International Symposium on Hardware-Oriented Security and Trust","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5108624758","display_name":"Lakshmi Ramakrishnan","orcid":null},"institutions":[{"id":"https://openalex.org/I1335490905","display_name":"Synopsys (Switzerland)","ror":"https://ror.org/03mb54f81","country_code":"CH","type":"company","lineage":["https://openalex.org/I1335490905","https://openalex.org/I4210088951"]},{"id":"https://openalex.org/I4210088951","display_name":"Synopsys (United States)","ror":"https://ror.org/013by2m91","country_code":"US","type":"company","lineage":["https://openalex.org/I4210088951"]},{"id":"https://openalex.org/I63135867","display_name":"University of Cincinnati","ror":"https://ror.org/01e3m7079","country_code":"US","type":"education","lineage":["https://openalex.org/I63135867"]}],"countries":["CH","US"],"is_corresponding":false,"raw_author_name":"Lakshmi Narasimhan Ramakrishnan","raw_affiliation_strings":["Synopsys","Digital Design Environments Laboratory, School of Electronics and Computing Systems, University of Cincinnati, Cincinnati, OH, USA","Synopsys, Inc., USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Synopsys","institution_ids":["https://openalex.org/I1335490905"]},{"raw_affiliation_string":"Digital Design Environments Laboratory, School of Electronics and Computing Systems, University of Cincinnati, Cincinnati, OH, USA","institution_ids":["https://openalex.org/I63135867"]},{"raw_affiliation_string":"Synopsys, Inc., USA","institution_ids":["https://openalex.org/I4210088951"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5084123515","display_name":"Manoj Chakkaravarthy","orcid":"https://orcid.org/0000-0003-2543-1619"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]},{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]},{"id":"https://openalex.org/I63135867","display_name":"University of Cincinnati","ror":"https://ror.org/01e3m7079","country_code":"US","type":"education","lineage":["https://openalex.org/I63135867"]}],"countries":["GB","US"],"is_corresponding":false,"raw_author_name":"Manoj Chakkaravarthy","raw_affiliation_strings":["Intel","Digital Design Environments Laboratory, School of Electronics and Computing Systems, University of Cincinnati, Cincinnati, OH, USA","Intel Corporation, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel","institution_ids":["https://openalex.org/I4210158342"]},{"raw_affiliation_string":"Digital Design Environments Laboratory, School of Electronics and Computing Systems, University of Cincinnati, Cincinnati, OH, USA","institution_ids":["https://openalex.org/I63135867"]},{"raw_affiliation_string":"Intel Corporation, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5052813899","display_name":"Antarpreet Singh Manchanda","orcid":null},"institutions":[{"id":"https://openalex.org/I4210127875","display_name":"Nvidia (United States)","ror":"https://ror.org/03jdj4y14","country_code":"US","type":"company","lineage":["https://openalex.org/I4210127875"]},{"id":"https://openalex.org/I63135867","display_name":"University of Cincinnati","ror":"https://ror.org/01e3m7079","country_code":"US","type":"education","lineage":["https://openalex.org/I63135867"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Antarpreet Singh Manchanda","raw_affiliation_strings":["NVIDIA","NVIDIA, USA","Digital Design Environments Laboratory, School of Electronics and Computing Systems, University of Cincinnati, Cincinnati, OH, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"NVIDIA","institution_ids":[]},{"raw_affiliation_string":"NVIDIA, USA","institution_ids":["https://openalex.org/I4210127875"]},{"raw_affiliation_string":"Digital Design Environments Laboratory, School of Electronics and Computing Systems, University of Cincinnati, Cincinnati, OH, USA","institution_ids":["https://openalex.org/I63135867"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5086398848","display_name":"Mike Borowczak","orcid":"https://orcid.org/0000-0001-9409-8245"},"institutions":[{"id":"https://openalex.org/I63135867","display_name":"University of Cincinnati","ror":"https://ror.org/01e3m7079","country_code":"US","type":"education","lineage":["https://openalex.org/I63135867"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Mike Borowczak","raw_affiliation_strings":["Digital Design Environments Lab, School of Electronics and Computing Systems, University of Cincinnati, Cincinnati, Ohio 45221-0030","Digital Design Environments Laboratory, School of Electronics and Computing Systems, University of Cincinnati, Cincinnati, OH, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Digital Design Environments Lab, School of Electronics and Computing Systems, University of Cincinnati, Cincinnati, Ohio 45221-0030","institution_ids":["https://openalex.org/I63135867"]},{"raw_affiliation_string":"Digital Design Environments Laboratory, School of Electronics and Computing Systems, University of Cincinnati, Cincinnati, OH, USA","institution_ids":["https://openalex.org/I63135867"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5040975645","display_name":"Ranga Vemuri","orcid":"https://orcid.org/0000-0002-4903-2746"},"institutions":[{"id":"https://openalex.org/I63135867","display_name":"University of Cincinnati","ror":"https://ror.org/01e3m7079","country_code":"US","type":"education","lineage":["https://openalex.org/I63135867"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ranga Vemuri","raw_affiliation_strings":["Digital Design Environments Lab, School of Electronics and Computing Systems, University of Cincinnati, Cincinnati, Ohio 45221-0030","Digital Design Environments Laboratory, School of Electronics and Computing Systems, University of Cincinnati, Cincinnati, OH, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Digital Design Environments Lab, School of Electronics and Computing Systems, University of Cincinnati, Cincinnati, Ohio 45221-0030","institution_ids":["https://openalex.org/I63135867"]},{"raw_affiliation_string":"Digital Design Environments Laboratory, School of Electronics and Computing Systems, University of Cincinnati, Cincinnati, OH, USA","institution_ids":["https://openalex.org/I63135867"]}]}],"institutions":[],"countries_distinct_count":3,"institutions_distinct_count":5,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":4.4228,"has_fulltext":false,"cited_by_count":21,"citation_normalized_percentile":{"value":0.94185681,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"31","last_page":"36"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10951","display_name":"Cryptographic Implementations and Security","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10951","display_name":"Cryptographic Implementations and Security","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11424","display_name":"Security and Verification in Computing","score":0.9950000047683716,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.6785039901733398},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.609944224357605},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.6046474575996399},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5999448299407959},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5980169177055359},{"id":"https://openalex.org/keywords/resistor\u2013transistor-logic","display_name":"Resistor\u2013transistor logic","score":0.5952572822570801},{"id":"https://openalex.org/keywords/differential","display_name":"Differential (mechanical device)","score":0.5028714537620544},{"id":"https://openalex.org/keywords/dynamic-logic","display_name":"Dynamic logic (digital electronics)","score":0.4838815927505493},{"id":"https://openalex.org/keywords/power-analysis","display_name":"Power analysis","score":0.45304301381111145},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.44855058193206787},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4317575693130493},{"id":"https://openalex.org/keywords/diode\u2013transistor-logic","display_name":"Diode\u2013transistor logic","score":0.4226342439651489},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4112958312034607},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.258340984582901},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2391906976699829},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.22173243761062622},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.2174762785434723},{"id":"https://openalex.org/keywords/cryptography","display_name":"Cryptography","score":0.09685930609703064}],"concepts":[{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.6785039901733398},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.609944224357605},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.6046474575996399},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5999448299407959},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5980169177055359},{"id":"https://openalex.org/C180405849","wikidata":"https://www.wikidata.org/wiki/Q173464","display_name":"Resistor\u2013transistor logic","level":5,"score":0.5952572822570801},{"id":"https://openalex.org/C93226319","wikidata":"https://www.wikidata.org/wiki/Q193137","display_name":"Differential (mechanical device)","level":2,"score":0.5028714537620544},{"id":"https://openalex.org/C2777796570","wikidata":"https://www.wikidata.org/wiki/Q2351326","display_name":"Dynamic logic (digital electronics)","level":4,"score":0.4838815927505493},{"id":"https://openalex.org/C71743495","wikidata":"https://www.wikidata.org/wiki/Q2845210","display_name":"Power analysis","level":3,"score":0.45304301381111145},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.44855058193206787},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4317575693130493},{"id":"https://openalex.org/C118759142","wikidata":"https://www.wikidata.org/wiki/Q173475","display_name":"Diode\u2013transistor logic","level":5,"score":0.4226342439651489},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4112958312034607},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.258340984582901},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2391906976699829},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.22173243761062622},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2174762785434723},{"id":"https://openalex.org/C178489894","wikidata":"https://www.wikidata.org/wiki/Q8789","display_name":"Cryptography","level":2,"score":0.09685930609703064},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0},{"id":"https://openalex.org/C146978453","wikidata":"https://www.wikidata.org/wiki/Q3798668","display_name":"Aerospace engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/hst.2012.6224315","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hst.2012.6224315","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE International Symposium on Hardware-Oriented Security and Trust","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.5699999928474426}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W1481250","https://openalex.org/W200116028","https://openalex.org/W1519539754","https://openalex.org/W1522953023","https://openalex.org/W1560093457","https://openalex.org/W1602420333","https://openalex.org/W1613874182","https://openalex.org/W1989903442","https://openalex.org/W1998633879","https://openalex.org/W2080267935","https://openalex.org/W2096490242","https://openalex.org/W2109396078","https://openalex.org/W2123955266","https://openalex.org/W2144630005","https://openalex.org/W2154909745","https://openalex.org/W2155383060","https://openalex.org/W2199322517","https://openalex.org/W4231098049","https://openalex.org/W4234360786","https://openalex.org/W6683178885"],"related_works":["https://openalex.org/W2021357106","https://openalex.org/W2017528947","https://openalex.org/W2096007426","https://openalex.org/W1495073259","https://openalex.org/W2155174752","https://openalex.org/W2991771859","https://openalex.org/W2158157809","https://openalex.org/W2561751396","https://openalex.org/W2142702094","https://openalex.org/W2127151832"],"abstract_inverted_index":{"The":[0],"emergence":[1],"and":[2,7,35,37,62,70,89,93],"proliferation":[3],"of":[4,58],"Smart":[5],"Cards":[6],"other":[8],"security-centric":[9],"technologies":[10],"require":[11],"ongoing":[12],"advancement":[13],"in":[14,41,86,98],"secure-IC":[15],"design.":[16],"We":[17,54],"propose":[18],"advanced":[19],"IC":[20],"protection":[21],"from":[22],"Differential":[23,38,68],"Power":[24],"Analysis":[25],"attack":[26],"though":[27],"a":[28,44,80,108],"hybrid-logic":[29],"style":[30],"based":[31,47],"on":[32,48,79],"Complementary":[33,74],"Pass-transistor":[34],"Dynamic":[36,67],"Logic":[39,75],"(DDL)":[40],"conjunction":[42],"with":[43,65],"synthesis":[45],"methodology":[46],"Reduced":[49],"Ordered":[50],"Binary":[51],"Decision":[52],"Diagrams.":[53],"demonstrate":[55],"the":[56,71],"capabilities":[57],"our":[59],"logic":[60],"cell":[61],"compare":[63],"it":[64],"Wave":[66],"Logic,":[69],"traditional":[72],"Standard":[73],"(SCMOS).":[76],"Experimental":[77],"results":[78],"DES":[81],"layout":[82],"show":[83],"significant":[84],"reduction":[85],"area":[87],"(43%)":[88],"total":[90],"power":[91,96],"(50%)":[92],"near":[94],"constant":[95],"consumption":[97],"every":[99],"cycle":[100],"when":[101],"compared":[102],"to":[103],"existing":[104],"DDL":[105],"styles":[106],"at":[107],"speed":[109],"penalty":[110],"(20%)":[111],"against":[112],"SCMOS.":[113]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":3},{"year":2019,"cited_by_count":4},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":2},{"year":2014,"cited_by_count":6},{"year":2013,"cited_by_count":3},{"year":2012,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}