{"id":"https://openalex.org/W4415250878","doi":"https://doi.org/10.1109/hpec67600.2025.11196564","title":"NTT-SAA: Exploring NTT Acceleration with 2-D Systolic Array Architecture on FPGAs","display_name":"NTT-SAA: Exploring NTT Acceleration with 2-D Systolic Array Architecture on FPGAs","publication_year":2025,"publication_date":"2025-09-15","ids":{"openalex":"https://openalex.org/W4415250878","doi":"https://doi.org/10.1109/hpec67600.2025.11196564"},"language":"en","primary_location":{"id":"doi:10.1109/hpec67600.2025.11196564","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hpec67600.2025.11196564","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE High Performance Extreme Computing Conference (HPEC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":null,"display_name":"Ashwajit Singh","orcid":null},"institutions":[{"id":"https://openalex.org/I162827531","display_name":"Indian Institute of Technology Bombay","ror":"https://ror.org/02qyf5152","country_code":"IN","type":"education","lineage":["https://openalex.org/I162827531"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Ashwajit Singh","raw_affiliation_strings":["Indian Institute of Technology Bombay,India"],"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology Bombay,India","institution_ids":["https://openalex.org/I162827531"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5004302525","display_name":"Zhihan Xu","orcid":"https://orcid.org/0009-0007-9644-6283"},"institutions":[{"id":"https://openalex.org/I1174212","display_name":"University of Southern California","ror":"https://ror.org/03taz7m60","country_code":"US","type":"education","lineage":["https://openalex.org/I1174212"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Zhihan Xu","raw_affiliation_strings":["University of Southern California,USA"],"affiliations":[{"raw_affiliation_string":"University of Southern California,USA","institution_ids":["https://openalex.org/I1174212"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5033166029","display_name":"Viktor K. Prasanna","orcid":"https://orcid.org/0000-0002-1609-8589"},"institutions":[{"id":"https://openalex.org/I1174212","display_name":"University of Southern California","ror":"https://ror.org/03taz7m60","country_code":"US","type":"education","lineage":["https://openalex.org/I1174212"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Viktor K. Prasanna","raw_affiliation_strings":["University of Southern California,USA"],"affiliations":[{"raw_affiliation_string":"University of Southern California,USA","institution_ids":["https://openalex.org/I1174212"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I162827531"],"apc_list":null,"apc_paid":null,"fwci":2.1258,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.88361803,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":96,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"7"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9947999715805054,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9947999715805054,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.958899974822998,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9538000226020813,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/systolic-array","display_name":"Systolic array","score":0.6668000221252441},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6543999910354614},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.5690000057220459},{"id":"https://openalex.org/keywords/polynomial","display_name":"Polynomial","score":0.5551999807357788},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.5483999848365784},{"id":"https://openalex.org/keywords/cryptography","display_name":"Cryptography","score":0.5328999757766724},{"id":"https://openalex.org/keywords/acceleration","display_name":"Acceleration","score":0.5049999952316284},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.4643000066280365}],"concepts":[{"id":"https://openalex.org/C150741067","wikidata":"https://www.wikidata.org/wiki/Q2377218","display_name":"Systolic array","level":3,"score":0.6668000221252441},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.656499981880188},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6543999910354614},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.5690000057220459},{"id":"https://openalex.org/C90119067","wikidata":"https://www.wikidata.org/wiki/Q43260","display_name":"Polynomial","level":2,"score":0.5551999807357788},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.5483999848365784},{"id":"https://openalex.org/C178489894","wikidata":"https://www.wikidata.org/wiki/Q8789","display_name":"Cryptography","level":2,"score":0.5328999757766724},{"id":"https://openalex.org/C117896860","wikidata":"https://www.wikidata.org/wiki/Q11376","display_name":"Acceleration","level":2,"score":0.5049999952316284},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.4643000066280365},{"id":"https://openalex.org/C311688","wikidata":"https://www.wikidata.org/wiki/Q2393193","display_name":"Time complexity","level":2,"score":0.4611000120639801},{"id":"https://openalex.org/C90673727","wikidata":"https://www.wikidata.org/wiki/Q901718","display_name":"Product (mathematics)","level":2,"score":0.4449000060558319},{"id":"https://openalex.org/C2780595030","wikidata":"https://www.wikidata.org/wiki/Q3860309","display_name":"Multiplication (music)","level":2,"score":0.4253999888896942},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.41179999709129333},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.3578000068664551},{"id":"https://openalex.org/C200288055","wikidata":"https://www.wikidata.org/wiki/Q2621792","display_name":"Element (criminal law)","level":2,"score":0.34769999980926514},{"id":"https://openalex.org/C13164978","wikidata":"https://www.wikidata.org/wiki/Q600158","display_name":"Hardware acceleration","level":3,"score":0.34299999475479126},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3395000100135803},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3296000063419342},{"id":"https://openalex.org/C179799912","wikidata":"https://www.wikidata.org/wiki/Q205084","display_name":"Computational complexity theory","level":2,"score":0.32179999351501465},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3125},{"id":"https://openalex.org/C203062551","wikidata":"https://www.wikidata.org/wiki/Q201339","display_name":"Public-key cryptography","level":3,"score":0.3109999895095825},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2989000082015991},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.28870001435279846},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.2709999978542328},{"id":"https://openalex.org/C459310","wikidata":"https://www.wikidata.org/wiki/Q117801","display_name":"Computational science","level":1,"score":0.2524000108242035}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/hpec67600.2025.11196564","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hpec67600.2025.11196564","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE High Performance Extreme Computing Conference (HPEC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":35,"referenced_works":["https://openalex.org/W179223734","https://openalex.org/W1483075820","https://openalex.org/W2031533839","https://openalex.org/W2415881634","https://openalex.org/W2866028610","https://openalex.org/W2953289753","https://openalex.org/W2979557494","https://openalex.org/W3005730048","https://openalex.org/W3013093367","https://openalex.org/W3065439923","https://openalex.org/W3116367236","https://openalex.org/W3165659700","https://openalex.org/W3185075495","https://openalex.org/W3207326900","https://openalex.org/W3213528054","https://openalex.org/W3216360301","https://openalex.org/W4225468027","https://openalex.org/W4225682136","https://openalex.org/W4226216812","https://openalex.org/W4226334377","https://openalex.org/W4229014338","https://openalex.org/W4281792301","https://openalex.org/W4285264388","https://openalex.org/W4367358287","https://openalex.org/W4386825228","https://openalex.org/W4389159461","https://openalex.org/W4393144920","https://openalex.org/W4400234368","https://openalex.org/W4400488260","https://openalex.org/W4401163376","https://openalex.org/W4402194615","https://openalex.org/W4405942354","https://openalex.org/W4406257892","https://openalex.org/W4407953952","https://openalex.org/W4409685327"],"related_works":[],"abstract_inverted_index":{"Number":[0],"Theoretic":[1],"Transform":[2],"(NTT)":[3],"is":[4],"a":[5,20,54,63,80,93,141],"key":[6],"operation":[7],"for":[8,26,57,118],"efficient":[9],"polynomial":[10,43,120],"multiplication":[11],"in":[12],"lattice-based":[13],"cryptographic":[14],"schemes.":[15],"This":[16],"paper":[17],"explores":[18],"using":[19],"2-D":[21,64],"Systolic":[22],"Array":[23],"Architecture":[24],"(SAA)":[25],"accelerating":[27],"the":[28,49,59,76,109,114,126],"NTT.":[29],"The":[30],"architecture":[31],"offers":[32],"inherent":[33],"regularity,":[34],"scalability,":[35],"and":[36,96],"flexibility,":[37],"allowing":[38],"it":[39],"to":[40,48,71,102,146],"support":[41,75],"various":[42,134],"sizes":[44,70],"without":[45],"requiring":[46],"modifications":[47],"design.":[50],"Specifically,":[51],"we":[52,78,91,112],"introduce":[53],"formal":[55],"methodology":[56],"mapping":[58],"NTT":[60],"computation":[61],"onto":[62],"systolic":[65],"array,":[66],"considering":[67],"small":[68],"array":[69,105],"ensure":[72],"scalability.":[73],"To":[74],"mapping,":[77],"design":[79],"novel":[81],"processing":[82],"element":[83],"that":[84,125],"efficiently":[85],"enables":[86],"tile-based":[87],"computation.":[88],"In":[89],"addition,":[90],"develop":[92],"performance":[94],"model":[95],"conduct":[97],"Design":[98],"Space":[99],"Exploration":[100],"(DSE)":[101],"identify":[103],"optimal":[104],"dimensions.":[106],"Guided":[107],"by":[108],"DSE":[110],"insights,":[111],"implement":[113],"accelerator,":[115],"named":[116],"NTT-SAA,":[117],"different":[119],"sizes.":[121],"Evaluation":[122],"results":[123],"show":[124],"NTT-SAA":[127],"family":[128],"can":[129],"achieve":[130],"1.4\u00d7\u20132.1\u00d7":[131],"speedups":[132],"across":[133],"Post-Quantum":[135],"Cryptography":[136],"(PQC)":[137],"protocols":[138],"while":[139],"maintaining":[140],"comparable":[142],"Area-Time":[143],"Product":[144],"(ATP)":[145],"state-of-the-art":[147],"designs.":[148]},"counts_by_year":[{"year":2026,"cited_by_count":1}],"updated_date":"2026-04-21T08:09:41.155169","created_date":"2025-10-16T00:00:00"}
