{"id":"https://openalex.org/W4390188259","doi":"https://doi.org/10.1109/hpec58863.2023.10363546","title":"An Analysis of Accelerator Data-Transfer Modes in NoC-Based SoC Architectures","display_name":"An Analysis of Accelerator Data-Transfer Modes in NoC-Based SoC Architectures","publication_year":2023,"publication_date":"2023-09-25","ids":{"openalex":"https://openalex.org/W4390188259","doi":"https://doi.org/10.1109/hpec58863.2023.10363546"},"language":"en","primary_location":{"id":"doi:10.1109/hpec58863.2023.10363546","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hpec58863.2023.10363546","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 IEEE High Performance Extreme Computing Conference (HPEC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5080149424","display_name":"Kuan-Lin Chiu","orcid":"https://orcid.org/0000-0002-4892-9711"},"institutions":[{"id":"https://openalex.org/I78577930","display_name":"Columbia University","ror":"https://ror.org/00hj8s172","country_code":"US","type":"education","lineage":["https://openalex.org/I78577930"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Kuan-Lin Chiu","raw_affiliation_strings":["Columbia University,Department of Computer Science,New York,U.S.A","Department of Computer Science, Columbia University, New York, U.S.A"],"affiliations":[{"raw_affiliation_string":"Columbia University,Department of Computer Science,New York,U.S.A","institution_ids":["https://openalex.org/I78577930"]},{"raw_affiliation_string":"Department of Computer Science, Columbia University, New York, U.S.A","institution_ids":["https://openalex.org/I78577930"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5027759717","display_name":"Davide Giri","orcid":"https://orcid.org/0000-0003-4101-4516"},"institutions":[{"id":"https://openalex.org/I78577930","display_name":"Columbia University","ror":"https://ror.org/00hj8s172","country_code":"US","type":"education","lineage":["https://openalex.org/I78577930"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Davide Giri","raw_affiliation_strings":["Columbia University,Department of Computer Science,New York,U.S.A","Department of Computer Science, Columbia University, New York, U.S.A"],"affiliations":[{"raw_affiliation_string":"Columbia University,Department of Computer Science,New York,U.S.A","institution_ids":["https://openalex.org/I78577930"]},{"raw_affiliation_string":"Department of Computer Science, Columbia University, New York, U.S.A","institution_ids":["https://openalex.org/I78577930"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5041117548","display_name":"Luca Piccolboni","orcid":"https://orcid.org/0000-0003-0094-4960"},"institutions":[{"id":"https://openalex.org/I78577930","display_name":"Columbia University","ror":"https://ror.org/00hj8s172","country_code":"US","type":"education","lineage":["https://openalex.org/I78577930"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Luca Piccolboni","raw_affiliation_strings":["Columbia University,Department of Computer Science,New York,U.S.A","Department of Computer Science, Columbia University, New York, U.S.A"],"affiliations":[{"raw_affiliation_string":"Columbia University,Department of Computer Science,New York,U.S.A","institution_ids":["https://openalex.org/I78577930"]},{"raw_affiliation_string":"Department of Computer Science, Columbia University, New York, U.S.A","institution_ids":["https://openalex.org/I78577930"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5009992367","display_name":"Luca P. Carloni","orcid":"https://orcid.org/0000-0001-5600-8931"},"institutions":[{"id":"https://openalex.org/I78577930","display_name":"Columbia University","ror":"https://ror.org/00hj8s172","country_code":"US","type":"education","lineage":["https://openalex.org/I78577930"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Luca P. Carloni","raw_affiliation_strings":["Columbia University,Department of Computer Science,New York,U.S.A","Department of Computer Science, Columbia University, New York, U.S.A"],"affiliations":[{"raw_affiliation_string":"Columbia University,Department of Computer Science,New York,U.S.A","institution_ids":["https://openalex.org/I78577930"]},{"raw_affiliation_string":"Department of Computer Science, Columbia University, New York, U.S.A","institution_ids":["https://openalex.org/I78577930"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5080149424"],"corresponding_institution_ids":["https://openalex.org/I78577930"],"apc_list":null,"apc_paid":null,"fwci":0.924,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.74026382,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"7"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8301470875740051},{"id":"https://openalex.org/keywords/thread","display_name":"Thread (computing)","score":0.7791965007781982},{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.6479096412658691},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5635625720024109},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.540294349193573},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5306728482246399},{"id":"https://openalex.org/keywords/efficient-energy-use","display_name":"Efficient energy use","score":0.5237748026847839},{"id":"https://openalex.org/keywords/data-transmission","display_name":"Data transmission","score":0.5189585089683533},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.43891599774360657},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.41666221618652344},{"id":"https://openalex.org/keywords/memory-architecture","display_name":"Memory architecture","score":0.41044795513153076},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.35048454999923706},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.2084469497203827},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.1877082884311676}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8301470875740051},{"id":"https://openalex.org/C138101251","wikidata":"https://www.wikidata.org/wiki/Q213092","display_name":"Thread (computing)","level":2,"score":0.7791965007781982},{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.6479096412658691},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5635625720024109},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.540294349193573},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5306728482246399},{"id":"https://openalex.org/C2742236","wikidata":"https://www.wikidata.org/wiki/Q924713","display_name":"Efficient energy use","level":2,"score":0.5237748026847839},{"id":"https://openalex.org/C557945733","wikidata":"https://www.wikidata.org/wiki/Q389772","display_name":"Data transmission","level":2,"score":0.5189585089683533},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.43891599774360657},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.41666221618652344},{"id":"https://openalex.org/C2779602883","wikidata":"https://www.wikidata.org/wiki/Q15544750","display_name":"Memory architecture","level":2,"score":0.41044795513153076},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.35048454999923706},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.2084469497203827},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.1877082884311676},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/hpec58863.2023.10363546","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hpec58863.2023.10363546","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 IEEE High Performance Extreme Computing Conference (HPEC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G5686897425","display_name":null,"funder_award_id":"W911NF-19-1-0476","funder_id":"https://openalex.org/F4320338281","funder_display_name":"Army Research Office"}],"funders":[{"id":"https://openalex.org/F4320332180","display_name":"Defense Advanced Research Projects Agency","ror":"https://ror.org/02caytj08"},{"id":"https://openalex.org/F4320338281","display_name":"Army Research Office","ror":"https://ror.org/05epdh915"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":24,"referenced_works":["https://openalex.org/W1982947349","https://openalex.org/W1996109622","https://openalex.org/W2019254738","https://openalex.org/W2047128179","https://openalex.org/W2085125624","https://openalex.org/W2089162427","https://openalex.org/W2091158003","https://openalex.org/W2128317332","https://openalex.org/W2150871235","https://openalex.org/W2284169075","https://openalex.org/W2397193845","https://openalex.org/W2769815320","https://openalex.org/W2771210328","https://openalex.org/W2884159178","https://openalex.org/W2936567838","https://openalex.org/W2980104813","https://openalex.org/W3002174694","https://openalex.org/W3036079062","https://openalex.org/W3036715599","https://openalex.org/W3081627712","https://openalex.org/W3101558675","https://openalex.org/W3104714893","https://openalex.org/W3116643785","https://openalex.org/W4252622709"],"related_works":["https://openalex.org/W2058965144","https://openalex.org/W2164382479","https://openalex.org/W2146343568","https://openalex.org/W98480971","https://openalex.org/W2150291671","https://openalex.org/W2013643406","https://openalex.org/W2027972911","https://openalex.org/W2157978810","https://openalex.org/W2597809628","https://openalex.org/W2011616113"],"abstract_inverted_index":{"Data":[0],"movement":[1,41],"is":[2,42],"a":[3,13,32,58,99,133],"key":[4],"factor":[5],"impacting":[6],"the":[7,22,39,48,62,89,106],"performance":[8],"of":[9,24,61,101,132],"hardware":[10],"accelerators.":[11],"In":[12],"complex":[14],"SoC":[15],"architecture,":[16],"multiple":[17],"accelerators":[18],"compete":[19],"for":[20,80,129],"accessing":[21],"resources":[23],"on-chip":[25],"communication":[26],"and":[27,70,83,94,112,121],"off-chip":[28],"memory":[29],"interfaces.":[30],"For":[31],"program":[33],"that":[34,50,128],"invokes":[35],"many":[36],"accelerators,":[37],"orchestrating":[38],"data":[40],"critically":[43],"important":[44],"to":[45,104],"avoid":[46],"degrading":[47],"speedup":[49],"each":[51],"standalone":[52],"accelerator":[53],"can":[54],"achieve.":[55],"We":[56,74,87,126],"present":[57],"comparative":[59],"analysis":[60],"two":[63,115],"main":[64],"data-transfer":[65,107],"modes":[66,108],"among":[67],"accelerators:":[68],"memory-based":[69,139],"point-to-point":[71],"(p2p)":[72],"communication.":[73,140],"describe":[75],"their":[76],"implementation":[77],"on":[78,91],"FPGA":[79],"both":[81],"single-thread":[82],"multi-thread":[84],"software":[85],"programs.":[86],"analyze":[88],"implications":[90],"programmability,":[92],"performance,":[93],"energy":[95],"efficiency":[96],"by":[97,113],"using":[98],"variety":[100],"synthetic":[102],"benchmarks":[103],"evaluate":[105],"in":[109],"different":[110],"scenarios":[111],"accelerating":[114],"real-world":[116],"image":[117],"processing":[118],"applications:":[119],"Nightvision":[120],"Wide-Area":[122],"Motion":[123],"Imagery":[124],"(WAMI).":[125],"demonstrate":[127],"various":[130],"configurations":[131],"tile-based":[134],"many-accelerator":[135],"SoC,":[136],"p2p":[137],"outperforms":[138]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
