{"id":"https://openalex.org/W4200112246","doi":"https://doi.org/10.1109/hpec49654.2021.9622832","title":"Toward HDL Extensions for Rapid AI/ML Accelerator Generation","display_name":"Toward HDL Extensions for Rapid AI/ML Accelerator Generation","publication_year":2021,"publication_date":"2021-09-20","ids":{"openalex":"https://openalex.org/W4200112246","doi":"https://doi.org/10.1109/hpec49654.2021.9622832"},"language":"en","primary_location":{"id":"doi:10.1109/hpec49654.2021.9622832","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hpec49654.2021.9622832","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 IEEE High Performance Extreme Computing Conference (HPEC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5004681193","display_name":"Ryan Kabrick","orcid":"https://orcid.org/0000-0001-8528-4812"},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Ryan Kabrick","raw_affiliation_strings":["Tactical Computing Labs, Newark, Delaware"],"affiliations":[{"raw_affiliation_string":"Tactical Computing Labs, Newark, Delaware","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5079595892","display_name":"John D. Leidel","orcid":"https://orcid.org/0000-0002-7567-8145"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"John Leidel","raw_affiliation_strings":["Tactical Computing Labs, Muenster, Texas"],"affiliations":[{"raw_affiliation_string":"Tactical Computing Labs, Muenster, Texas","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5103136279","display_name":"David Donofrio","orcid":"https://orcid.org/0000-0001-9197-2208"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"David Donofrio","raw_affiliation_strings":["Tactical Computing Labs, San Francisco, California"],"affiliations":[{"raw_affiliation_string":"Tactical Computing Labs, San Francisco, California","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5004681193"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.4606,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.61833386,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8770509362220764},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.8081926107406616},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.7033958435058594},{"id":"https://openalex.org/keywords/construct","display_name":"Construct (python library)","score":0.6144068837165833},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.49820470809936523},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.46715086698532104},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.4483024477958679},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.4218027591705322},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.284906804561615},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.16516342759132385}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8770509362220764},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.8081926107406616},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.7033958435058594},{"id":"https://openalex.org/C2780801425","wikidata":"https://www.wikidata.org/wiki/Q5164392","display_name":"Construct (python library)","level":2,"score":0.6144068837165833},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.49820470809936523},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.46715086698532104},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.4483024477958679},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.4218027591705322},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.284906804561615},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.16516342759132385}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/hpec49654.2021.9622832","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hpec49654.2021.9622832","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 IEEE High Performance Extreme Computing Conference (HPEC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.6399999856948853,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W1983394510","https://openalex.org/W2132729131","https://openalex.org/W2912012512","https://openalex.org/W2944703441","https://openalex.org/W3030108406","https://openalex.org/W4246166885"],"related_works":["https://openalex.org/W1761969858","https://openalex.org/W1998013902","https://openalex.org/W2391854357","https://openalex.org/W4238487776","https://openalex.org/W2550108858","https://openalex.org/W3114194214","https://openalex.org/W1781968824","https://openalex.org/W2132512458","https://openalex.org/W4247993032","https://openalex.org/W3145476088"],"abstract_inverted_index":{"StoneCutter,":[0],"a":[1,94,123,157,166],"language":[2,97,161,215],"construct":[3,98],"and":[4,29,40,43,116,162,176,205,220],"compiler":[5,112],"embedded":[6],"in":[7,61,119,187,248],"the":[8,21,62,86,103,130,134,153,159,184,207,211],"OpenSoC":[9],"System":[10,88],"Architect":[11,89],"family":[12],"of":[13,129,152],"tools,":[14,137],"is":[15,59],"designed":[16],"to":[17,23,50,72,78,101,121,182,189,209,217,232,238],"provide":[18],"software":[19],"architects":[20,206],"ability":[22,208],"rapidly":[24],"prototype":[25],"instruction":[26,74,115,169],"set":[27],"extensions":[28],"hardware":[30,243,250],"accelerators.":[31],"The":[32,109],"StoneCutter":[33,58,111,160,185,212],"compilation":[34,49,196],"flow":[35],"ingests":[36],"high":[37,124,213],"level":[38,214],"syntax":[39],"outputs":[41],"optimized":[42,198,226,241],"pipelined":[44],"Chisel":[45,126,136],"HDL":[46,56,127],"for":[47,105,173,194],"further":[48],"platform-specific":[51],"RTL.":[52,234],"However,":[53],"unlike":[54],"other":[55],"approaches,":[57],"rooted":[60],"notion":[63],"that":[64,69],"users":[65,138,204,237],"define":[66],"syntactic":[67],"blocks":[68],"map":[70],"directly":[71,231],"individual":[73,114],"definitions":[75],"as":[76,147,149],"opposed":[77],"classic":[79],"finite":[80],"state":[81],"machines.":[82],"When":[83],"integrated":[84],"with":[85,245],"adjacent":[87],"design":[90,171],"flow,":[91],"Stone-Cutter":[92],"provides":[93,165,203],"familiar,":[95],"C-like":[96],"by":[99],"which":[100],"develop":[102,218,251],"implementation":[104],"individual,":[106],"programmable":[107],"instructions.":[108,200],"LLVM-based":[110],"performs":[113],"whole-ISA":[117],"optimizations":[118],"order":[120,188],"generate":[122,141],"performance,":[125],"representation":[128],"target":[131,154,219],"design.":[132,155],"Utilizing":[133],"existing":[135],"can":[139],"also":[140],"C++":[142],"cycle":[143],"accurate":[144],"simulation":[145],"models":[146],"well":[148],"Verilog":[150],"representations":[151],"As":[156],"result,":[158],"associated":[163],"tooling":[164],"very":[167],"rapid,":[168],"set-centric":[170],"environment":[172],"rapid":[174],"development":[175],"experimentation.This":[177],"work":[178],"describes":[179],"initial":[180],"efforts":[181],"extend":[183],"infrastructure":[186],"encapsulate":[190],"linear":[191,227],"algebraic":[192,228],"constructs":[193,216,229],"direct":[195],"into":[197],"AI/ML":[199,223,242],"This":[201,235],"functionality":[202],"utilize":[210],"domain":[221],"specific":[222],"instructions":[224],"using":[225],"compiled":[230],"target-specific":[233],"enables":[236],"create":[239],"highly":[240],"implementations":[244],"minimal":[246],"effort":[247],"traditional":[249],"flows.":[252]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2021,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
