{"id":"https://openalex.org/W2902632257","doi":"https://doi.org/10.1109/hpec.2018.8547560","title":"GoblinCore-64: A RISC-V Based Architecture for Data Intensive Computing","display_name":"GoblinCore-64: A RISC-V Based Architecture for Data Intensive Computing","publication_year":2018,"publication_date":"2018-09-01","ids":{"openalex":"https://openalex.org/W2902632257","doi":"https://doi.org/10.1109/hpec.2018.8547560","mag":"2902632257"},"language":"en","primary_location":{"id":"doi:10.1109/hpec.2018.8547560","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hpec.2018.8547560","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE High Performance extreme Computing Conference (HPEC)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5079595892","display_name":"John D. Leidel","orcid":"https://orcid.org/0000-0002-7567-8145"},"institutions":[{"id":"https://openalex.org/I12315562","display_name":"Texas Tech University","ror":"https://ror.org/0405mnx93","country_code":"US","type":"education","lineage":["https://openalex.org/I12315562"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"John D. Leidel","raw_affiliation_strings":["Tactical Computing Labs, Texas Tech University, Muenster, Texas, US"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Tactical Computing Labs, Texas Tech University, Muenster, Texas, US","institution_ids":["https://openalex.org/I12315562"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100442245","display_name":"Xi Wang","orcid":"https://orcid.org/0000-0002-1998-6733"},"institutions":[{"id":"https://openalex.org/I12315562","display_name":"Texas Tech University","ror":"https://ror.org/0405mnx93","country_code":"US","type":"education","lineage":["https://openalex.org/I12315562"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Xi Wang","raw_affiliation_strings":["Department of Computer Science, Texas Tech Univeristy, Lubbock, Texas, US"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science, Texas Tech Univeristy, Lubbock, Texas, US","institution_ids":["https://openalex.org/I12315562"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5077521546","display_name":"Yong Chen","orcid":"https://orcid.org/0000-0002-9961-9051"},"institutions":[{"id":"https://openalex.org/I12315562","display_name":"Texas Tech University","ror":"https://ror.org/0405mnx93","country_code":"US","type":"education","lineage":["https://openalex.org/I12315562"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yong Chen","raw_affiliation_strings":["Department of Computer Science, Texas Tech Univeristy, Lubbock, Texas, US"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science, Texas Tech Univeristy, Lubbock, Texas, US","institution_ids":["https://openalex.org/I12315562"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I12315562"],"apc_list":null,"apc_paid":null,"fwci":0.4406,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.54063522,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"abs 1508 3619","issue":null,"first_page":"1","last_page":"8"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10101","display_name":"Cloud Computing and Resource Management","score":0.9959999918937683,"subfield":{"id":"https://openalex.org/subfields/1710","display_name":"Information Systems"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8757818341255188},{"id":"https://openalex.org/keywords/memory-hierarchy","display_name":"Memory hierarchy","score":0.6081916689872742},{"id":"https://openalex.org/keywords/working-set","display_name":"Working set","score":0.4975109398365021},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.482940137386322},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.46628355979919434},{"id":"https://openalex.org/keywords/concurrency","display_name":"Concurrency","score":0.45730477571487427},{"id":"https://openalex.org/keywords/uniform-memory-access","display_name":"Uniform memory access","score":0.4251856207847595},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.3508743643760681},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3423070013523102},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.3265058398246765},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.3090481758117676},{"id":"https://openalex.org/keywords/overlay","display_name":"Overlay","score":0.2278570532798767},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.14164727926254272}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8757818341255188},{"id":"https://openalex.org/C2778100165","wikidata":"https://www.wikidata.org/wiki/Q1589327","display_name":"Memory hierarchy","level":3,"score":0.6081916689872742},{"id":"https://openalex.org/C88196245","wikidata":"https://www.wikidata.org/wiki/Q8034984","display_name":"Working set","level":2,"score":0.4975109398365021},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.482940137386322},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.46628355979919434},{"id":"https://openalex.org/C193702766","wikidata":"https://www.wikidata.org/wiki/Q1414548","display_name":"Concurrency","level":2,"score":0.45730477571487427},{"id":"https://openalex.org/C51290061","wikidata":"https://www.wikidata.org/wiki/Q1936765","display_name":"Uniform memory access","level":4,"score":0.4251856207847595},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.3508743643760681},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3423070013523102},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.3265058398246765},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.3090481758117676},{"id":"https://openalex.org/C136085584","wikidata":"https://www.wikidata.org/wiki/Q910289","display_name":"Overlay","level":2,"score":0.2278570532798767},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.14164727926254272}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/hpec.2018.8547560","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hpec.2018.8547560","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE High Performance extreme Computing Conference (HPEC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.6100000143051147,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":25,"referenced_works":["https://openalex.org/W220440441","https://openalex.org/W826415870","https://openalex.org/W1252105715","https://openalex.org/W1807272711","https://openalex.org/W1978709910","https://openalex.org/W2004203489","https://openalex.org/W2024906372","https://openalex.org/W2053930610","https://openalex.org/W2055534506","https://openalex.org/W2081040934","https://openalex.org/W2090673788","https://openalex.org/W2107594045","https://openalex.org/W2114233691","https://openalex.org/W2137702271","https://openalex.org/W2139984346","https://openalex.org/W2157443293","https://openalex.org/W2163112135","https://openalex.org/W2169929427","https://openalex.org/W2533888780","https://openalex.org/W2759444369","https://openalex.org/W2766335550","https://openalex.org/W3011889816","https://openalex.org/W3138766643","https://openalex.org/W3138952164","https://openalex.org/W3169135813"],"related_works":["https://openalex.org/W2133121403","https://openalex.org/W2606565524","https://openalex.org/W4389476357","https://openalex.org/W2811273125","https://openalex.org/W4285361447","https://openalex.org/W4311294724","https://openalex.org/W254684032","https://openalex.org/W2115061140","https://openalex.org/W1542587432","https://openalex.org/W2916808240"],"abstract_inverted_index":{"Current":[0],"microprocessor":[1],"architectures":[2,21],"rely":[3],"upon":[4],"multi-level":[5],"data":[6,40,71],"caches":[7],"and":[8,101,113,132,146,164],"low":[9],"degrees":[10],"of":[11,18,54,95],"concurrency":[12,100,131],"to":[13,25,83,98,160],"solve":[14],"a":[15,65,78,84,92],"wide":[16],"range":[17],"applications.":[19],"These":[20],"are":[22],"well":[23],"suited":[24],"efficiently":[26],"executing":[27],"applications":[28,42],"that":[29,50,68,141,153],"support":[30,99,125],"memory":[31,45,56,80,105,128],"access":[32,44],"patterns":[33],"with":[34],"spatial":[35],"and/or":[36],"temporal":[37],"locality.":[38],"However,":[39],"intensive":[41,72],"often":[43],"in":[46],"an":[47,110],"irregular":[48],"manner":[49],"prevents":[51],"optimal":[52],"use":[53],"the":[55,147],"hierarchy.":[57],"In":[58],"this":[59],"work,":[60],"we":[61],"introduce":[62],"GoblinCore-64":[63],"(GC64),":[64],"novel":[66],"architecture":[67],"supports":[69],"large-scale":[70],"high":[73],"performance":[74],"computing":[75],"workloads":[76,157],"using":[77,109,138],"unique":[79],"hierarchy":[81,106],"coupled":[82],"latency-hiding":[85],"micro":[86],"architecture.":[87],"The":[88,104,119],"GC64":[89,137,154],"infrastructure":[90],"is":[91,107],"hierarchical":[93],"set":[94,123],"modules":[96],"designed":[97],"latency":[102],"hiding.":[103],"constructed":[108],"on-chip":[111],"scratchpad":[112],"Hybrid":[114],"Memory":[115],"Cube":[116],"3D":[117],"memories.":[118],"RISC-V":[120],"based":[121],"instruction":[122],"includes":[124],"for":[126],"scatter/gather":[127],"operations,":[129],"task":[130,133],"management.":[134],"We":[135,151],"demonstrate":[136],"standard":[139],"benchmarks":[140],"include":[142],"NAS,":[143],"HPCG,":[144],"BOTS":[145],"GAP":[148],"Benchmark":[149],"Suite.":[150],"find":[152],"accelerates":[155],"these":[156],"by":[158,167],"up":[159],"14X":[161],"per":[162],"core":[163],"improves":[165],"bandwidth":[166],"3.5X.":[168]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2018,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}