{"id":"https://openalex.org/W2903090374","doi":"https://doi.org/10.1109/hpec.2018.8547551","title":"An Access-Pattern-Aware On-Chip Vector Memory System with Automatic Loading for SIMD Architectures","display_name":"An Access-Pattern-Aware On-Chip Vector Memory System with Automatic Loading for SIMD Architectures","publication_year":2018,"publication_date":"2018-09-01","ids":{"openalex":"https://openalex.org/W2903090374","doi":"https://doi.org/10.1109/hpec.2018.8547551","mag":"2903090374"},"language":"en","primary_location":{"id":"doi:10.1109/hpec.2018.8547551","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hpec.2018.8547551","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE High Performance extreme Computing Conference (HPEC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5078443672","display_name":"Tong Geng","orcid":"https://orcid.org/0000-0002-3644-2922"},"institutions":[{"id":"https://openalex.org/I111088046","display_name":"Boston University","ror":"https://ror.org/05qwgg493","country_code":"US","type":"education","lineage":["https://openalex.org/I111088046"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Tong Geng","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Boston University, Boston, MA, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Boston University, Boston, MA, USA","institution_ids":["https://openalex.org/I111088046"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5004196694","display_name":"Erkan Diken","orcid":null},"institutions":[{"id":"https://openalex.org/I126520041","display_name":"University of Science and Technology of China","ror":"https://ror.org/04c4dkn09","country_code":"CN","type":"education","lineage":["https://openalex.org/I126520041","https://openalex.org/I19820366"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Erkan Diken","raw_affiliation_strings":["Department of Physics, University of Science and Technology of China, Hefei, China"],"affiliations":[{"raw_affiliation_string":"Department of Physics, University of Science and Technology of China, Hefei, China","institution_ids":["https://openalex.org/I126520041"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100734913","display_name":"Tianqi Wang","orcid":"https://orcid.org/0000-0002-5921-6565"},"institutions":[{"id":"https://openalex.org/I126520041","display_name":"University of Science and Technology of China","ror":"https://ror.org/04c4dkn09","country_code":"CN","type":"education","lineage":["https://openalex.org/I126520041","https://openalex.org/I19820366"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Tianqi Wang","raw_affiliation_strings":["Department of Physics, University of Science and Technology of China, Hefei, China"],"affiliations":[{"raw_affiliation_string":"Department of Physics, University of Science and Technology of China, Hefei, China","institution_ids":["https://openalex.org/I126520041"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5109220541","display_name":"L. J\u00f3\u017awiak","orcid":null},"institutions":[{"id":"https://openalex.org/I83019370","display_name":"Eindhoven University of Technology","ror":"https://ror.org/02c2kyt77","country_code":"NL","type":"education","lineage":["https://openalex.org/I83019370"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"Lech Jozwiak","raw_affiliation_strings":["Department of Electrical Engineering, Eindhoven University of Technology, Eindhoven, Netherlands"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Eindhoven University of Technology, Eindhoven, Netherlands","institution_ids":["https://openalex.org/I83019370"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5021051610","display_name":"Martin Herbordt","orcid":"https://orcid.org/0000-0002-3443-9113"},"institutions":[{"id":"https://openalex.org/I111088046","display_name":"Boston University","ror":"https://ror.org/05qwgg493","country_code":"US","type":"education","lineage":["https://openalex.org/I111088046"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Martin Herbordt","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Boston University, Boston, MA, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Boston University, Boston, MA, USA","institution_ids":["https://openalex.org/I111088046"]}]}],"institutions":[],"countries_distinct_count":3,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5078443672"],"corresponding_institution_ids":["https://openalex.org/I111088046"],"apc_list":null,"apc_paid":null,"fwci":0.7881,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.72330601,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":95},"biblio":{"volume":"32","issue":null,"first_page":"1","last_page":"7"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8643470406532288},{"id":"https://openalex.org/keywords/simd","display_name":"SIMD","score":0.703773021697998},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.5458945035934448},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5241192579269409},{"id":"https://openalex.org/keywords/bottleneck","display_name":"Bottleneck","score":0.5116291642189026},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.4881156384944916},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.48438817262649536},{"id":"https://openalex.org/keywords/flat-memory-model","display_name":"Flat memory model","score":0.46577924489974976},{"id":"https://openalex.org/keywords/uniform-memory-access","display_name":"Uniform memory access","score":0.4508974552154541},{"id":"https://openalex.org/keywords/registered-memory","display_name":"Registered memory","score":0.44085970520973206},{"id":"https://openalex.org/keywords/energy-consumption","display_name":"Energy consumption","score":0.4380134046077728},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4223843514919281},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.42166879773139954},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.36041826009750366},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.27145516872406006},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.11271637678146362}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8643470406532288},{"id":"https://openalex.org/C150552126","wikidata":"https://www.wikidata.org/wiki/Q339387","display_name":"SIMD","level":2,"score":0.703773021697998},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.5458945035934448},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5241192579269409},{"id":"https://openalex.org/C2780513914","wikidata":"https://www.wikidata.org/wiki/Q18210350","display_name":"Bottleneck","level":2,"score":0.5116291642189026},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.4881156384944916},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.48438817262649536},{"id":"https://openalex.org/C57863822","wikidata":"https://www.wikidata.org/wiki/Q905488","display_name":"Flat memory model","level":4,"score":0.46577924489974976},{"id":"https://openalex.org/C51290061","wikidata":"https://www.wikidata.org/wiki/Q1936765","display_name":"Uniform memory access","level":4,"score":0.4508974552154541},{"id":"https://openalex.org/C93446704","wikidata":"https://www.wikidata.org/wiki/Q449328","display_name":"Registered memory","level":3,"score":0.44085970520973206},{"id":"https://openalex.org/C2780165032","wikidata":"https://www.wikidata.org/wiki/Q16869822","display_name":"Energy consumption","level":2,"score":0.4380134046077728},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4223843514919281},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.42166879773139954},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.36041826009750366},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.27145516872406006},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.11271637678146362},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C18903297","wikidata":"https://www.wikidata.org/wiki/Q7150","display_name":"Ecology","level":1,"score":0.0}],"mesh":[],"locations_count":6,"locations":[{"id":"doi:10.1109/hpec.2018.8547551","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hpec.2018.8547551","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE High Performance extreme Computing Conference (HPEC)","raw_type":"proceedings-article"},{"id":"pmh:oai:pure.tue.nl:openaire_cris_publications/a84f965e-8ea4-4328-811c-3abf13d2e998","is_oa":false,"landing_page_url":"https://research.tue.nl/en/publications/a84f965e-8ea4-4328-811c-3abf13d2e998","pdf_url":null,"source":{"id":"https://openalex.org/S4406922641","display_name":"TU/e Research Portal","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Geng, T, Diken, E, Wang, T, Jozwiak, L & Herbordt, M 2018, An access-pattern-aware on-chip vector memory system with automatic loading for SIMD architectures. in 2018 IEEE High Performance Extreme Computing Conference, HPEC 2018., 8547551, Institute of Electrical and Electronics Engineers, Piscataway, 2018 IEEE High Performance Extreme Computing Conference, HPEC 2018, Waltham, United States, 25/09/18. https://doi.org/10.1109/HPEC.2018.8547551","raw_type":"info:eu-repo/semantics/publishedVersion"},{"id":"pmh:909543","is_oa":false,"landing_page_url":"http://library.tue.nl/csp/dare/LinkToRepository.csp?recordnumber=909543","pdf_url":null,"source":{"id":"https://openalex.org/S4406923046","display_name":"TU/e Research Portal (Eindhoven University of Technology)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":""},{"id":"pmh:oai:library.tue.nl:909543","is_oa":false,"landing_page_url":"http://repository.tue.nl/909543","pdf_url":null,"source":{"id":"https://openalex.org/S4406923046","display_name":"TU/e Research Portal (Eindhoven University of Technology)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":""},{"id":"pmh:oai:pure.tue.nl:publications/a84f965e-8ea4-4328-811c-3abf13d2e998","is_oa":false,"landing_page_url":"http://www.scopus.com/inward/record.url?scp=85060076269&partnerID=8YFLogxK","pdf_url":null,"source":{"id":"https://openalex.org/S4406922641","display_name":"TU/e Research Portal","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Geng, T, Diken, E, Wang, T, Jozwiak, L & Herbordt, M 2018, An access-pattern-aware on-chip vector memory system with automatic loading for SIMD architectures. in 2018 IEEE High Performance Extreme Computing Conference, HPEC 2018., 8547551, Institute of Electrical and Electronics Engineers, Piscataway, 2018 IEEE High Performance Extreme Computing Conference, HPEC 2018, Waltham, United States, 25/09/18. https://doi.org/10.1109/HPEC.2018.8547551","raw_type":"info:eu-repo/semantics/publishedVersion"},{"id":"pmh:tue:oai:pure.tue.nl:publications/a84f965e-8ea4-4328-811c-3abf13d2e998","is_oa":false,"landing_page_url":"https://research.tue.nl/nl/publications/a84f965e-8ea4-4328-811c-3abf13d2e998","pdf_url":null,"source":{"id":"https://openalex.org/S4306401843","display_name":"Data Archiving and Networked Services (DANS)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1322597698","host_organization_name":"Royal Netherlands Academy of Arts and Sciences","host_organization_lineage":["https://openalex.org/I1322597698"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"2018 IEEE High Performance Extreme Computing Conference, HPEC 2018","raw_type":"info:eu-repo/semantics/conferencepaper"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.9100000262260437,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":26,"referenced_works":["https://openalex.org/W41695356","https://openalex.org/W101196121","https://openalex.org/W1966400000","https://openalex.org/W1984854771","https://openalex.org/W1998441272","https://openalex.org/W2011889208","https://openalex.org/W2033279368","https://openalex.org/W2099610600","https://openalex.org/W2102543317","https://openalex.org/W2116963870","https://openalex.org/W2121011198","https://openalex.org/W2159124195","https://openalex.org/W2164390225","https://openalex.org/W2168434186","https://openalex.org/W2546299555","https://openalex.org/W2579648009","https://openalex.org/W2605251767","https://openalex.org/W2768065515","https://openalex.org/W2891890103","https://openalex.org/W2902769771","https://openalex.org/W3148705872","https://openalex.org/W4229654654","https://openalex.org/W4233447799","https://openalex.org/W4238973935","https://openalex.org/W6601671223","https://openalex.org/W6756480441"],"related_works":["https://openalex.org/W2587873888","https://openalex.org/W2155373950","https://openalex.org/W2044064773","https://openalex.org/W2041174925","https://openalex.org/W2782503170","https://openalex.org/W3108993429","https://openalex.org/W4233816696","https://openalex.org/W1993089791","https://openalex.org/W2903168712","https://openalex.org/W1707075782"],"abstract_inverted_index":{"Single-Instruction-Multiple-Data":[0],"(SIMD)":[1],"architectures":[2],"are":[3],"widely":[4],"used":[5],"to":[6,93],"accelerate":[7],"applications":[8],"involving":[9],"Data-Level":[10],"Parallelism":[11],"(DLP);":[12],"the":[13,18,34,48,81,94,124,134],"on-chip":[14,25,35],"memory":[15,36,57,61,70,78],"system":[16,37,62],"facilitates":[17],"communication":[19],"between":[20],"Processing":[21],"Elements":[22],"(PE)":[23],"and":[24,50,72,105,112,132],"vector":[26,55],"memory.":[27],"It":[28],"is":[29,38,110],"observed":[30],"that":[31,120],"inefficiency":[32],"of":[33,52,64,103,126],"often":[39],"a":[40],"computational":[41],"bottleneck.":[42],"In":[43],"this":[44],"paper,":[45],"we":[46],"describe":[47],"design":[49,109,122],"implementation":[51],"an":[53,68,73],"efficient":[54],"data":[56,82,90],"system.":[58],"The":[59,77,85,107],"proposed":[60,108],"consists":[63],"two":[65],"novel":[66],"parts:":[67],"access-pattern-aware":[69],"controller":[71,79],"automatic":[74,86],"loading":[75,87],"mechanism.":[76],"reduces":[80,133],"reorganization":[83],"overheads.":[84],"mechanism":[88],"loads":[89],"automatically":[91],"according":[92],"access":[95],"patterns":[96],"without":[97],"load":[98],"instructions.":[99],"This":[100],"eliminates":[101],"overhead":[102],"fetching":[104],"decoding.":[106],"implemented":[111],"synthesized":[113],"with":[114],"Cadence":[115],"tools.":[116],"Experimental":[117],"results":[118],"demonstrate":[119],"our":[121],"improves":[123],"performance":[125],"8":[127],"application":[128],"kernels":[129],"by":[130,137],"44%":[131],"energy":[135],"consumption":[136],"26%,":[138],"on":[139],"average.":[140]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":1}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}
