{"id":"https://openalex.org/W2903523299","doi":"https://doi.org/10.1109/hpec.2018.8547545","title":"Exploiting GPU with 3D Stacked Memory to Boost Performance for Data-Intensive Applications","display_name":"Exploiting GPU with 3D Stacked Memory to Boost Performance for Data-Intensive Applications","publication_year":2018,"publication_date":"2018-09-01","ids":{"openalex":"https://openalex.org/W2903523299","doi":"https://doi.org/10.1109/hpec.2018.8547545","mag":"2903523299"},"language":"en","primary_location":{"id":"doi:10.1109/hpec.2018.8547545","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hpec.2018.8547545","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE High Performance extreme Computing Conference (HPEC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5020805029","display_name":"Hao Wen","orcid":"https://orcid.org/0000-0002-1424-9910"},"institutions":[{"id":"https://openalex.org/I184840846","display_name":"Virginia Commonwealth University","ror":"https://ror.org/02nkdxk79","country_code":"US","type":"education","lineage":["https://openalex.org/I184840846"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Hao Wen","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Virginia Commonwealth University, Richmond, VA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Virginia Commonwealth University, Richmond, VA","institution_ids":["https://openalex.org/I184840846"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100441535","display_name":"Wei Zhang","orcid":"https://orcid.org/0000-0001-9405-447X"},"institutions":[{"id":"https://openalex.org/I184840846","display_name":"Virginia Commonwealth University","ror":"https://ror.org/02nkdxk79","country_code":"US","type":"education","lineage":["https://openalex.org/I184840846"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Wei Zhang","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Virginia Commonwealth University, Richmond, VA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Virginia Commonwealth University, Richmond, VA","institution_ids":["https://openalex.org/I184840846"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I184840846"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.16257067,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":91,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8010010719299316},{"id":"https://openalex.org/keywords/bottleneck","display_name":"Bottleneck","score":0.7943830490112305},{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.7692552804946899},{"id":"https://openalex.org/keywords/memory-bandwidth","display_name":"Memory bandwidth","score":0.6717900037765503},{"id":"https://openalex.org/keywords/cas-latency","display_name":"CAS latency","score":0.5812411308288574},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5531675219535828},{"id":"https://openalex.org/keywords/registered-memory","display_name":"Registered memory","score":0.49443578720092773},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4649582803249359},{"id":"https://openalex.org/keywords/merge","display_name":"Merge (version control)","score":0.4624969959259033},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4538222551345825},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.4450497031211853},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.4006570875644684},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.36581194400787354},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.2888320982456207},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.11831027269363403}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8010010719299316},{"id":"https://openalex.org/C2780513914","wikidata":"https://www.wikidata.org/wiki/Q18210350","display_name":"Bottleneck","level":2,"score":0.7943830490112305},{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.7692552804946899},{"id":"https://openalex.org/C188045654","wikidata":"https://www.wikidata.org/wiki/Q17148339","display_name":"Memory bandwidth","level":2,"score":0.6717900037765503},{"id":"https://openalex.org/C189930140","wikidata":"https://www.wikidata.org/wiki/Q1112878","display_name":"CAS latency","level":4,"score":0.5812411308288574},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5531675219535828},{"id":"https://openalex.org/C93446704","wikidata":"https://www.wikidata.org/wiki/Q449328","display_name":"Registered memory","level":3,"score":0.49443578720092773},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4649582803249359},{"id":"https://openalex.org/C197129107","wikidata":"https://www.wikidata.org/wiki/Q1921621","display_name":"Merge (version control)","level":2,"score":0.4624969959259033},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4538222551345825},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.4450497031211853},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.4006570875644684},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.36581194400787354},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.2888320982456207},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.11831027269363403},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/hpec.2018.8547545","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hpec.2018.8547545","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE High Performance extreme Computing Conference (HPEC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.7599999904632568,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1981943579","https://openalex.org/W2071208935","https://openalex.org/W2080592089","https://openalex.org/W2082375193","https://openalex.org/W2118703320","https://openalex.org/W2122636510","https://openalex.org/W2131413854","https://openalex.org/W2143807959","https://openalex.org/W2250217037","https://openalex.org/W2556370608","https://openalex.org/W2952128411","https://openalex.org/W3139689176","https://openalex.org/W4297923268"],"related_works":["https://openalex.org/W1976244802","https://openalex.org/W3008068282","https://openalex.org/W2557931434","https://openalex.org/W2065759842","https://openalex.org/W4393076761","https://openalex.org/W2023569851","https://openalex.org/W2132401245","https://openalex.org/W3089341786","https://openalex.org/W2041015482","https://openalex.org/W2267274498"],"abstract_inverted_index":{"An":[0],"increasing":[1],"number":[2,14],"of":[3,15,65,76],"applications":[4],"are":[5],"using":[6,38],"GPUs":[7],"for":[8],"acceleration.":[9],"Due":[10],"to":[11,32,43,82,86],"the":[12,18,30,34,51,60,77,89],"massive":[13],"memory":[16,28,68,84],"accesses,":[17],"traditional":[19,52],"DRAM":[20,78],"becomes":[21],"a":[22],"bandwidth":[23,35,63],"bottleneck.":[24],"The":[25],"3D":[26,66],"stacked":[27,67],"gives":[29],"potential":[31],"alleviate":[33],"bottleneck":[36],"by":[37],"through":[39],"silicon":[40],"vias":[41],"(TSVs)":[42],"deliver":[44],"much":[45],"higher":[46],"on-chip":[47],"bus":[48],"width":[49],"than":[50],"off-chip":[53],"interface.":[54],"In":[55,71],"this":[56],"paper,":[57],"we":[58,73],"evaluate":[59],"latency":[61],"and":[62],"benefits":[64],"on":[69],"GPUs.":[70],"addition,":[72],"take":[74],"advantage":[75],"row":[79],"buffer":[80],"locality":[81],"merge":[83],"requests":[85],"further":[87],"improve":[88],"performance.":[90]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":1},{"year":2023,"cited_by_count":2}],"updated_date":"2026-06-26T08:34:08.712188","created_date":"2025-10-10T00:00:00"}
