{"id":"https://openalex.org/W2558083466","doi":"https://doi.org/10.1109/hpec.2016.7761627","title":"Optimizing simulation speed of FPGA model-based synthesis","display_name":"Optimizing simulation speed of FPGA model-based synthesis","publication_year":2016,"publication_date":"2016-09-01","ids":{"openalex":"https://openalex.org/W2558083466","doi":"https://doi.org/10.1109/hpec.2016.7761627","mag":"2558083466"},"language":"en","primary_location":{"id":"doi:10.1109/hpec.2016.7761627","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hpec.2016.7761627","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE High Performance Extreme Computing Conference (HPEC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5037403960","display_name":"Jeffrey Caldwell","orcid":null},"institutions":[{"id":"https://openalex.org/I1306686416","display_name":"RTX (United States)","ror":"https://ror.org/0354t7b78","country_code":"US","type":"company","lineage":["https://openalex.org/I1306686416"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Jeffrey Caldwell","raw_affiliation_strings":["Raytheon Company Space and Airborne Systems, EI Segundo, CA"],"affiliations":[{"raw_affiliation_string":"Raytheon Company Space and Airborne Systems, EI Segundo, CA","institution_ids":["https://openalex.org/I1306686416"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5054222231","display_name":"Bo Marr","orcid":null},"institutions":[{"id":"https://openalex.org/I1306686416","display_name":"RTX (United States)","ror":"https://ror.org/0354t7b78","country_code":"US","type":"company","lineage":["https://openalex.org/I1306686416"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Bo Marr","raw_affiliation_strings":["Raytheon Company Space and Airborne Systems, EI Segundo, CA"],"affiliations":[{"raw_affiliation_string":"Raytheon Company Space and Airborne Systems, EI Segundo, CA","institution_ids":["https://openalex.org/I1306686416"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5061674037","display_name":"David E. Bloom","orcid":"https://orcid.org/0000-0003-3731-3345"},"institutions":[{"id":"https://openalex.org/I1306686416","display_name":"RTX (United States)","ror":"https://ror.org/0354t7b78","country_code":"US","type":"company","lineage":["https://openalex.org/I1306686416"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"David Bloom","raw_affiliation_strings":["Raytheon Company Space and Airborne Systems, EI Segundo, CA"],"affiliations":[{"raw_affiliation_string":"Raytheon Company Space and Airborne Systems, EI Segundo, CA","institution_ids":["https://openalex.org/I1306686416"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5104068702","display_name":"Dan R. Thompson","orcid":null},"institutions":[{"id":"https://openalex.org/I1306686416","display_name":"RTX (United States)","ror":"https://ror.org/0354t7b78","country_code":"US","type":"company","lineage":["https://openalex.org/I1306686416"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Dan Thompson","raw_affiliation_strings":["Raytheon Company Space and Airborne Systems, EI Segundo, CA"],"affiliations":[{"raw_affiliation_string":"Raytheon Company Space and Airborne Systems, EI Segundo, CA","institution_ids":["https://openalex.org/I1306686416"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5037403960"],"corresponding_institution_ids":["https://openalex.org/I1306686416"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.13682528,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"4","issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12810","display_name":"Real-time simulation and control systems","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.781813383102417},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7794147729873657},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7440757751464844},{"id":"https://openalex.org/keywords/abstraction","display_name":"Abstraction","score":0.6163550615310669},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.5892120599746704},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5479221343994141},{"id":"https://openalex.org/keywords/hardware-description-language","display_name":"Hardware description language","score":0.5466176271438599},{"id":"https://openalex.org/keywords/behavioral-modeling","display_name":"Behavioral modeling","score":0.5132946372032166},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4650479555130005},{"id":"https://openalex.org/keywords/exploit","display_name":"Exploit","score":0.43752166628837585},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.42055219411849976},{"id":"https://openalex.org/keywords/code","display_name":"Code (set theory)","score":0.4164441227912903},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.38282373547554016},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.21987226605415344},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.19585317373275757},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.1479719877243042},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.11895737051963806}],"concepts":[{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.781813383102417},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7794147729873657},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7440757751464844},{"id":"https://openalex.org/C124304363","wikidata":"https://www.wikidata.org/wiki/Q673661","display_name":"Abstraction","level":2,"score":0.6163550615310669},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.5892120599746704},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5479221343994141},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.5466176271438599},{"id":"https://openalex.org/C78639753","wikidata":"https://www.wikidata.org/wiki/Q3318160","display_name":"Behavioral modeling","level":2,"score":0.5132946372032166},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4650479555130005},{"id":"https://openalex.org/C165696696","wikidata":"https://www.wikidata.org/wiki/Q11287","display_name":"Exploit","level":2,"score":0.43752166628837585},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.42055219411849976},{"id":"https://openalex.org/C2776760102","wikidata":"https://www.wikidata.org/wiki/Q5139990","display_name":"Code (set theory)","level":3,"score":0.4164441227912903},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.38282373547554016},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.21987226605415344},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.19585317373275757},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.1479719877243042},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.11895737051963806},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C111472728","wikidata":"https://www.wikidata.org/wiki/Q9471","display_name":"Epistemology","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/hpec.2016.7761627","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hpec.2016.7761627","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE High Performance Extreme Computing Conference (HPEC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5099999904632568,"display_name":"Decent work and economic growth","id":"https://metadata.un.org/sdg/8"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W2043858766","https://openalex.org/W2116344719","https://openalex.org/W2129183345","https://openalex.org/W2166029537","https://openalex.org/W4236089896"],"related_works":["https://openalex.org/W2110818533","https://openalex.org/W1917852300","https://openalex.org/W2384838054","https://openalex.org/W1843355381","https://openalex.org/W1492116303","https://openalex.org/W2069295582","https://openalex.org/W2077870657","https://openalex.org/W2164733497","https://openalex.org/W2363829830","https://openalex.org/W2115658098"],"abstract_inverted_index":{"FPGA":[0,13,36],"capacity":[1],"is":[2,24,31,77,87],"quickly":[3],"outpacing":[4],"designer's":[5],"productivity":[6],"and":[7,61,65,68,75,97,107,134],"limiting":[8],"the":[9,70,85],"ability":[10],"to":[11,90,124,129,138],"exploit":[12],"processing":[14],"resources.":[15],"Model-based":[16],"synthesis,":[17],"where":[18],"a":[19,43],"high":[20],"level":[21,81],"behavioral":[22,60,105],"model":[23,86],"used":[25],"for":[26],"fast":[27],"design":[28,63],"iteration,":[29],"which":[30],"then":[32],"synthesizable":[33,120],"directly":[34,119],"into":[35],"object":[37],"code":[38],"has":[39],"been":[40,54],"proposed":[41],"as":[42],"solution.":[44],"Several":[45],"orders":[46],"of":[47,59,82,84,118],"magnitude":[48],"difference":[49],"in":[50],"simulation":[51,73,95,126],"speed":[52,74,96],"have":[53],"observed":[55],"between":[56,72,93],"different":[57],"variants":[58],"model-based":[62,140],"tools":[64],"thus":[66],"understanding":[67],"optimizing":[69],"trade":[71],"abstraction":[76,83],"critical.":[78],"A":[79],"dynamic":[80],"also":[88],"examined":[89],"study":[91],"trades":[92],"abstraction,":[94],"accuracy.":[98],"Mathworks'":[99],"HDL":[100,132],"Coder":[101],"tool,":[102],"hand":[103,130],"optimized":[104,109],"VHDL,":[106],"vendor":[108],"Xilinx's":[110],"System":[111],"Generator":[112],"are":[113,116],"compared.":[114],"Results":[115],"shown":[117],"models":[121],"with":[122],"up":[123],"894X":[125],"speedups":[127,136],"compared":[128,137],"coded":[131],"simulations":[133],"4356X":[135],"other":[139],"synthesis":[141],"tools.":[142]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}