{"id":"https://openalex.org/W2046159926","doi":"https://doi.org/10.1109/hpec.2014.7040995","title":"Accelerating SAR processing on COTS FPGA hardware using C-to-gates design tools","display_name":"Accelerating SAR processing on COTS FPGA hardware using C-to-gates design tools","publication_year":2014,"publication_date":"2014-09-01","ids":{"openalex":"https://openalex.org/W2046159926","doi":"https://doi.org/10.1109/hpec.2014.7040995","mag":"2046159926"},"language":"en","primary_location":{"id":"doi:10.1109/hpec.2014.7040995","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hpec.2014.7040995","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 IEEE High Performance Extreme Computing Conference (HPEC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5113681691","display_name":"Raymond R. Hoare","orcid":null},"institutions":[{"id":"https://openalex.org/I36343934","display_name":"Concurrent Technologies Corporation","ror":"https://ror.org/00sgv1989","country_code":"US","type":"nonprofit","lineage":["https://openalex.org/I36343934"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Raymond R. Hoare","raw_affiliation_strings":["Concurrent EDA, LLC, Pittsburgh, PA","Concurrent EDA, LLC, Pittsburgh, PA, USA"],"affiliations":[{"raw_affiliation_string":"Concurrent EDA, LLC, Pittsburgh, PA","institution_ids":["https://openalex.org/I36343934"]},{"raw_affiliation_string":"Concurrent EDA, LLC, Pittsburgh, PA, USA","institution_ids":["https://openalex.org/I36343934"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5058321838","display_name":"Denis Smetana","orcid":null},"institutions":[{"id":"https://openalex.org/I4210133886","display_name":"Curtiss-Wright (United States)","ror":"https://ror.org/03h6x6x11","country_code":"US","type":"company","lineage":["https://openalex.org/I4210133886"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Denis Smetana","raw_affiliation_strings":["Curtiss-Wright, Ashburn, VA","Curtiss-Wright, Ashburn, VA, USA"],"affiliations":[{"raw_affiliation_string":"Curtiss-Wright, Ashburn, VA","institution_ids":["https://openalex.org/I4210133886"]},{"raw_affiliation_string":"Curtiss-Wright, Ashburn, VA, USA","institution_ids":["https://openalex.org/I4210133886"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5113681691"],"corresponding_institution_ids":["https://openalex.org/I36343934"],"apc_list":null,"apc_paid":null,"fwci":0.3085,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.59309091,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9980000257492065,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8317726850509644},{"id":"https://openalex.org/keywords/firmware","display_name":"Firmware","score":0.724190354347229},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6504783034324646},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.649113655090332},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.4516831338405609},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4452046751976013},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3607120215892792}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8317726850509644},{"id":"https://openalex.org/C67212190","wikidata":"https://www.wikidata.org/wiki/Q104851","display_name":"Firmware","level":2,"score":0.724190354347229},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6504783034324646},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.649113655090332},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.4516831338405609},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4452046751976013},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3607120215892792}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/hpec.2014.7040995","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hpec.2014.7040995","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 IEEE High Performance Extreme Computing Conference (HPEC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6200000047683716,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":2,"referenced_works":["https://openalex.org/W309890564","https://openalex.org/W2493328864"],"related_works":["https://openalex.org/W1876592433","https://openalex.org/W2083269738","https://openalex.org/W2390365330","https://openalex.org/W2380628475","https://openalex.org/W2359368668","https://openalex.org/W2130731919","https://openalex.org/W2055097091","https://openalex.org/W2367409037","https://openalex.org/W2373226583","https://openalex.org/W2388210573"],"abstract_inverted_index":{"Next":[0],"generation":[1],"radar":[2],"systems":[3],"require":[4],"that":[5,34,52,81],"massive":[6],"computations":[7],"be":[8],"performed":[9],"in":[10],"real":[11],"time":[12],"and":[13,17,66,83,117],"have":[14],"size,":[15],"weight":[16],"power":[18],"restrictions.":[19],"Increasingly,":[20],"cost":[21],"is":[22,43,74],"also":[23],"playing":[24],"a":[25,60,105],"major":[26,32],"role.":[27],"This":[28,90],"paper":[29,91],"introduces":[30],"two":[31],"innovations":[33],"help":[35],"meet":[36],"these":[37],"SWaP-C":[38],"requirements.":[39],"The":[40,71],"first":[41],"innovation":[42,73],"the":[44,130],"COTS":[45],"OpenVPX":[46],"board":[47],"from":[48],"Curtiss-Wright":[49],"called":[50],"CHAMP-FX4":[51,136],"contains":[53],"three":[54],"large":[55],"Virtex":[56],"7":[57],"FPGAs":[58],"with":[59],"total":[61],"of":[62,108,122,129],"10,800":[63],"DSP":[64],"Slices":[65],"4,410":[67],"on-chip":[68],"Block":[69],"RAMs.":[70],"second":[72],"Concurrent":[75],"EDA's":[76],"FPGA":[77,88,132],"design":[78],"automation":[79],"tools":[80],"analyze":[82],"synthesize":[84],"C/C++":[85],"into":[86],"high-performance":[87],"firmware.":[89],"describes":[92],"how":[93],"SAR":[94],"processing":[95],"was":[96,140],"accelerated":[97],"by":[98],"39":[99],"to":[100],"46":[101],"times":[102],"faster":[103],"than":[104,120],"single":[106],"core":[107],"an":[109],"Intel":[110],"Core":[111],"i7":[112],"CPU":[113],"running":[114],"at":[115],"3.6GHz":[116],"consumed":[118],"less":[119],"half":[121],"one":[123],"FPGA,":[124],"1/6":[125],"<sup":[126],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[127],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">th</sup>":[128],"available":[131],"area":[133],"on":[134],"Curtiss-Wright's":[135],"hardware.":[137],"Total":[138],"design-time":[139],"6":[141],"weeks.":[142]},"counts_by_year":[{"year":2020,"cited_by_count":1},{"year":2016,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}