{"id":"https://openalex.org/W2049036888","doi":"https://doi.org/10.1109/hpec.2013.6670321","title":"Block Processor: A resource-distributed architecture","display_name":"Block Processor: A resource-distributed architecture","publication_year":2013,"publication_date":"2013-09-01","ids":{"openalex":"https://openalex.org/W2049036888","doi":"https://doi.org/10.1109/hpec.2013.6670321","mag":"2049036888"},"language":"en","primary_location":{"id":"doi:10.1109/hpec.2013.6670321","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hpec.2013.6670321","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE High Performance Extreme Computing Conference (HPEC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5004837462","display_name":"Zeke Wang","orcid":"https://orcid.org/0000-0001-8550-9241"},"institutions":[{"id":"https://openalex.org/I76130692","display_name":"Zhejiang University","ror":"https://ror.org/00a2xv884","country_code":"CN","type":"education","lineage":["https://openalex.org/I76130692"]},{"id":"https://openalex.org/I55712492","display_name":"Zhejiang University of Technology","ror":"https://ror.org/02djqfd08","country_code":"CN","type":"education","lineage":["https://openalex.org/I55712492"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Zeke Wang","raw_affiliation_strings":["Institute of Digital Technology and Instrument, Zhejiang University, Hangzhou, China","Institute of Digital Technology and Instruments, Zhejiang University, Hangzhou, China"],"affiliations":[{"raw_affiliation_string":"Institute of Digital Technology and Instrument, Zhejiang University, Hangzhou, China","institution_ids":["https://openalex.org/I55712492"]},{"raw_affiliation_string":"Institute of Digital Technology and Instruments, Zhejiang University, Hangzhou, China","institution_ids":["https://openalex.org/I76130692"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5043895556","display_name":"Feng Yu","orcid":"https://orcid.org/0000-0002-9740-2537"},"institutions":[{"id":"https://openalex.org/I76130692","display_name":"Zhejiang University","ror":"https://ror.org/00a2xv884","country_code":"CN","type":"education","lineage":["https://openalex.org/I76130692"]},{"id":"https://openalex.org/I55712492","display_name":"Zhejiang University of Technology","ror":"https://ror.org/02djqfd08","country_code":"CN","type":"education","lineage":["https://openalex.org/I55712492"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Feng Yu","raw_affiliation_strings":["Institute of Digital Technology and Instrument, Zhejiang University, Hangzhou, China","Institute of Digital Technology and Instruments, Zhejiang University, Hangzhou, China"],"affiliations":[{"raw_affiliation_string":"Institute of Digital Technology and Instrument, Zhejiang University, Hangzhou, China","institution_ids":["https://openalex.org/I55712492"]},{"raw_affiliation_string":"Institute of Digital Technology and Instruments, Zhejiang University, Hangzhou, China","institution_ids":["https://openalex.org/I76130692"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100372152","display_name":"Xue Liu","orcid":"https://orcid.org/0000-0001-5252-3442"},"institutions":[{"id":"https://openalex.org/I9224756","display_name":"Northeastern University","ror":"https://ror.org/03awzbc87","country_code":"CN","type":"education","lineage":["https://openalex.org/I9224756"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xue Liu","raw_affiliation_strings":["Institute of Cyber-Physical Systems Engineering, Northeastern University, Shenyang, China","Inst. of Cyber-Phys. Syst. Eng., Northeastern Univ., Shenyang, China"],"affiliations":[{"raw_affiliation_string":"Institute of Cyber-Physical Systems Engineering, Northeastern University, Shenyang, China","institution_ids":["https://openalex.org/I9224756"]},{"raw_affiliation_string":"Inst. of Cyber-Phys. Syst. Eng., Northeastern Univ., Shenyang, China","institution_ids":["https://openalex.org/I9224756"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5004837462"],"corresponding_institution_ids":["https://openalex.org/I55712492","https://openalex.org/I76130692"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.11275779,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8188092708587646},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.6431288123130798},{"id":"https://openalex.org/keywords/coprocessor","display_name":"Coprocessor","score":0.6215294599533081},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5985287427902222},{"id":"https://openalex.org/keywords/operand","display_name":"Operand","score":0.5866065621376038},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.4630572497844696},{"id":"https://openalex.org/keywords/chaining","display_name":"Chaining","score":0.43285125494003296},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.39863574504852295},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.33442917466163635},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.25237125158309937}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8188092708587646},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.6431288123130798},{"id":"https://openalex.org/C86111242","wikidata":"https://www.wikidata.org/wiki/Q859595","display_name":"Coprocessor","level":2,"score":0.6215294599533081},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5985287427902222},{"id":"https://openalex.org/C55526617","wikidata":"https://www.wikidata.org/wiki/Q719375","display_name":"Operand","level":2,"score":0.5866065621376038},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.4630572497844696},{"id":"https://openalex.org/C49020025","wikidata":"https://www.wikidata.org/wiki/Q1059099","display_name":"Chaining","level":2,"score":0.43285125494003296},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.39863574504852295},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.33442917466163635},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.25237125158309937},{"id":"https://openalex.org/C15744967","wikidata":"https://www.wikidata.org/wiki/Q9418","display_name":"Psychology","level":0,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C542102704","wikidata":"https://www.wikidata.org/wiki/Q183257","display_name":"Psychotherapist","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/hpec.2013.6670321","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hpec.2013.6670321","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE High Performance Extreme Computing Conference (HPEC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1555915743","https://openalex.org/W1564901611","https://openalex.org/W1969648707","https://openalex.org/W1977933385","https://openalex.org/W2097959379","https://openalex.org/W2146449469","https://openalex.org/W2148041475","https://openalex.org/W2152077064","https://openalex.org/W2152687294","https://openalex.org/W2725179571","https://openalex.org/W2913795363","https://openalex.org/W3014482339","https://openalex.org/W4247008581","https://openalex.org/W4255632552","https://openalex.org/W6828640377"],"related_works":["https://openalex.org/W2556282987","https://openalex.org/W1533508804","https://openalex.org/W2050923821","https://openalex.org/W2506885233","https://openalex.org/W1876282873","https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W1608572506","https://openalex.org/W4401155055","https://openalex.org/W2165099691"],"abstract_inverted_index":{"We":[0,76],"present":[1],"the":[2,44,54,69,78,85,88,110,118,127,131],"architecture":[3,67],"of":[4,36,43,120],"Block":[5,22,45,79,101,144],"Processor,":[6],"task-level":[7],"coprocessor,":[8],"to":[9,103],"execute":[10],"vectorizable":[11],"computing":[12,128],"task":[13],"migrated":[14],"from":[15],"main":[16],"processor":[17],"via":[18],"command":[19],"bus.":[20],"The":[21,47,66],"Processor":[23,80],"is":[24],"designed":[25],"around":[26],"32":[27],"high-MVL":[28],"block":[29,70,96],"registers,":[30,71],"which":[31,81],"can":[32],"be":[33,40,104],"direct":[34],"operands":[35],"vector":[37,121],"instruction":[38],"and":[39,57,73,107,113,124],"local":[41],"cache":[42],"Processor.":[46,145],"corresponding":[48],"unique":[49],"conflict-solving":[50],"mechanism":[51],"scales":[52],"with":[53],"various":[55],"implementations":[56],"easily":[58],"supports":[59],"chaining":[60,112],"by":[61],"adding":[62],"extra":[63],"execution":[64],"states.":[65],"distributes":[68,91],"ALUs":[72],"control":[74],"logic.":[75],"implement":[77],"maps":[82],"efficiently":[83],"into":[84],"FPGA":[86,89,100],"since":[87],"also":[90],"its":[92],"inner":[93],"resource.":[94],"Each":[95],"register":[97],"requires":[98],"two":[99],"RAM":[102],"2-read-1-write-port,":[105],"1024-depth":[106],"32-bit-width.":[108],"With":[109,130],"enhanced":[111],"decoupling,":[114],"it":[115],"might":[116],"hinder":[117],"latency":[119],"memory":[122],"instructions":[123],"then":[125],"sustain":[126],"abilities.":[129],"little":[132],"resource":[133],"occupied,":[134],"1024-point":[135],"radix-2":[136],"DIF":[137],"FFT":[138],"costs":[139],"11348":[140],"cycles":[141],"on":[142],"one":[143]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
