{"id":"https://openalex.org/W2521026526","doi":"https://doi.org/10.1109/hpcsim.2016.7568325","title":"A wide-range clock signal generation scheme for speed grading of a logic core","display_name":"A wide-range clock signal generation scheme for speed grading of a logic core","publication_year":2016,"publication_date":"2016-07-01","ids":{"openalex":"https://openalex.org/W2521026526","doi":"https://doi.org/10.1109/hpcsim.2016.7568325","mag":"2521026526"},"language":"en","primary_location":{"id":"doi:10.1109/hpcsim.2016.7568325","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hpcsim.2016.7568325","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 International Conference on High Performance Computing &amp; Simulation (HPCS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5085636078","display_name":"Shi\u2010Yu Huang","orcid":"https://orcid.org/0000-0002-3721-987X"},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Shi-Yu Huang","raw_affiliation_strings":["Electrical Engineering Department, National Tsing Hua University, Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical Engineering Department, National Tsing Hua University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I25846049"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5080659678","display_name":"Tzu-Heng Huang","orcid":null},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Tzu-Heng Huang","raw_affiliation_strings":["Electrical Engineering Department, National Tsing Hua University, Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical Engineering Department, National Tsing Hua University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I25846049"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5064587514","display_name":"Kun-Han Tsai","orcid":"https://orcid.org/0000-0001-8919-8663"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Kun-Han Tsai","raw_affiliation_strings":["Silicon Test Solutions, Mentor Graphics, Wilsonville, Oregon, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Silicon Test Solutions, Mentor Graphics, Wilsonville, Oregon, USA","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5020407423","display_name":"Wu-Tung Cheng","orcid":"https://orcid.org/0000-0001-6327-2394"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Wu-Tung Cheng","raw_affiliation_strings":["Silicon Test Solutions, Mentor Graphics, Wilsonville, Oregon, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Silicon Test Solutions, Mentor Graphics, Wilsonville, Oregon, USA","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"125","last_page":"129"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.635200560092926},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5131831765174866},{"id":"https://openalex.org/keywords/single-core","display_name":"Single-core","score":0.49729064106941223},{"id":"https://openalex.org/keywords/process-variation","display_name":"Process variation","score":0.47844579815864563},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4708057641983032},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.43611377477645874},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4346396327018738},{"id":"https://openalex.org/keywords/process-corners","display_name":"Process corners","score":0.4345747232437134},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.4220942258834839},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.3558623790740967},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3394221067428589},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.24864643812179565},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.20445945858955383},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.19221720099449158},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.1910320222377777},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.08985093235969543}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.635200560092926},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5131831765174866},{"id":"https://openalex.org/C2780365336","wikidata":"https://www.wikidata.org/wiki/Q25047934","display_name":"Single-core","level":2,"score":0.49729064106941223},{"id":"https://openalex.org/C93389723","wikidata":"https://www.wikidata.org/wiki/Q7247313","display_name":"Process variation","level":3,"score":0.47844579815864563},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4708057641983032},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.43611377477645874},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4346396327018738},{"id":"https://openalex.org/C192615534","wikidata":"https://www.wikidata.org/wiki/Q7247268","display_name":"Process corners","level":3,"score":0.4345747232437134},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.4220942258834839},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.3558623790740967},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3394221067428589},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.24864643812179565},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.20445945858955383},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.19221720099449158},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.1910320222377777},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.08985093235969543},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/hpcsim.2016.7568325","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hpcsim.2016.7568325","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 International Conference on High Performance Computing &amp; Simulation (HPCS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.7099999785423279}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1973730070","https://openalex.org/W1980288753","https://openalex.org/W2078267331","https://openalex.org/W2107203410","https://openalex.org/W2123145598","https://openalex.org/W2126281568","https://openalex.org/W2150534321","https://openalex.org/W2152321821","https://openalex.org/W2155452708","https://openalex.org/W2187247199","https://openalex.org/W2295397453","https://openalex.org/W6643657880"],"related_works":["https://openalex.org/W2525077515","https://openalex.org/W2118152793","https://openalex.org/W2141625582","https://openalex.org/W4388000032","https://openalex.org/W2162806231","https://openalex.org/W2080140894","https://openalex.org/W629662700","https://openalex.org/W2564437568","https://openalex.org/W2073479284","https://openalex.org/W2090769959"],"abstract_inverted_index":{"In":[0,44,89],"a":[1,46,51,59,84,100,111],"modern":[2],"multi-core":[3],"SoC,":[4],"the":[5,37,68,79],"Built-In":[6],"Speed":[7],"Grading":[8],"(BISG)":[9],"of":[10,29,83],"each":[11],"logic":[12,52,112],"core":[13,53,86,113],"is":[14],"often":[15],"necessary":[16],"in":[17,124],"order":[18],"to":[19,35,77],"ensure":[20],"an":[21,94],"adequate":[22],"operating":[23,81],"margin":[24],"for":[25,50],"accommodating":[26],"all":[27],"kinds":[28],"variation":[30],"(e.g.,":[31,64],"PVT":[32],"variation),":[33],"and":[34,122],"guide":[36],"dynamic":[38],"VDD":[39],"tuning":[40],"process":[41],"as":[42],"well.":[43],"general,":[45],"speed":[47,82,96],"grading":[48,97],"method":[49,98],"can":[54,109],"be":[55,116],"performed":[56],"by":[57],"repeating":[58],"specific":[60,85],"delay":[61],"test":[62,74],"session,":[63],"built-in":[65],"self-test":[66],"with":[67,72,118],"latch-off":[69],"capture":[70],"scheme),":[71],"varying":[73],"clock":[75,103],"frequencies":[76],"derive":[78],"maximum":[80],"under":[87],"testing.":[88],"this":[90],"paper,":[91],"we":[92],"propose":[93],"easy-to-use":[95],"featuring":[99],"wide-range":[101],"synthesizable":[102],"generation":[104],"scheme":[105],"so":[106],"that":[107,114],"it":[108],"support":[110],"could":[115],"used":[117],"different":[119,125],"supply":[120],"voltages":[121],"speeds":[123],"application":[126],"domains.":[127]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":2},{"year":2020,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
