{"id":"https://openalex.org/W2521023919","doi":"https://doi.org/10.1109/hpcsim.2016.7568324","title":"A Chip-level Redundant Threading (CRT) scheme for shared-memory protection","display_name":"A Chip-level Redundant Threading (CRT) scheme for shared-memory protection","publication_year":2016,"publication_date":"2016-07-01","ids":{"openalex":"https://openalex.org/W2521023919","doi":"https://doi.org/10.1109/hpcsim.2016.7568324","mag":"2521023919"},"language":"en","primary_location":{"id":"doi:10.1109/hpcsim.2016.7568324","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hpcsim.2016.7568324","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 International Conference on High Performance Computing &amp; Simulation (HPCS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5085639767","display_name":"Erol Koser","orcid":null},"institutions":[{"id":"https://openalex.org/I62916508","display_name":"Technical University of Munich","ror":"https://ror.org/02kkvpp62","country_code":"DE","type":"education","lineage":["https://openalex.org/I62916508"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Erol Koser","raw_affiliation_strings":["Institute for Integrated Systems, Technische Universit\u00e4t M\u00fcnchen, Germany"],"affiliations":[{"raw_affiliation_string":"Institute for Integrated Systems, Technische Universit\u00e4t M\u00fcnchen, Germany","institution_ids":["https://openalex.org/I62916508"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5023635046","display_name":"Korbinian Berthold","orcid":null},"institutions":[{"id":"https://openalex.org/I62916508","display_name":"Technical University of Munich","ror":"https://ror.org/02kkvpp62","country_code":"DE","type":"education","lineage":["https://openalex.org/I62916508"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Korbinian Berthold","raw_affiliation_strings":["Institute for Integrated Systems, Technische Universit\u00e4t M\u00fcnchen, Germany"],"affiliations":[{"raw_affiliation_string":"Institute for Integrated Systems, Technische Universit\u00e4t M\u00fcnchen, Germany","institution_ids":["https://openalex.org/I62916508"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5113779327","display_name":"Ravi Kumar Pujari","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Ravi Kumar Pujari","raw_affiliation_strings":["Technische Universitat Munchen, Munchen, Bayern, DE"],"affiliations":[{"raw_affiliation_string":"Technische Universitat Munchen, Munchen, Bayern, DE","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5005732789","display_name":"Walter Stechele","orcid":"https://orcid.org/0000-0002-7455-8483"},"institutions":[{"id":"https://openalex.org/I62916508","display_name":"Technical University of Munich","ror":"https://ror.org/02kkvpp62","country_code":"DE","type":"education","lineage":["https://openalex.org/I62916508"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Walter Stechele","raw_affiliation_strings":["Institute for Integrated Systems, Technische Universit\u00e4t M\u00fcnchen, Germany"],"affiliations":[{"raw_affiliation_string":"Institute for Integrated Systems, Technische Universit\u00e4t M\u00fcnchen, Germany","institution_ids":["https://openalex.org/I62916508"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5085639767"],"corresponding_institution_ids":["https://openalex.org/I62916508"],"apc_list":null,"apc_paid":null,"fwci":0.3675,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.66018673,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"116","last_page":"124"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.996999979019165,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9969000220298767,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6720421314239502},{"id":"https://openalex.org/keywords/threading","display_name":"Threading (protein sequence)","score":0.664605975151062},{"id":"https://openalex.org/keywords/scheme","display_name":"Scheme (mathematics)","score":0.5141823291778564},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4454265832901001},{"id":"https://openalex.org/keywords/memory-protection","display_name":"Memory protection","score":0.4229975640773773},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.37563958764076233},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.34348559379577637},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.2827904224395752},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2310241460800171},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.10388705134391785},{"id":"https://openalex.org/keywords/virtual-memory","display_name":"Virtual memory","score":0.08884561061859131},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.06202003359794617}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6720421314239502},{"id":"https://openalex.org/C200307862","wikidata":"https://www.wikidata.org/wiki/Q7797175","display_name":"Threading (protein sequence)","level":3,"score":0.664605975151062},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.5141823291778564},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4454265832901001},{"id":"https://openalex.org/C18131444","wikidata":"https://www.wikidata.org/wiki/Q163585","display_name":"Memory protection","level":5,"score":0.4229975640773773},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.37563958764076233},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.34348559379577637},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.2827904224395752},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2310241460800171},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.10388705134391785},{"id":"https://openalex.org/C76399640","wikidata":"https://www.wikidata.org/wiki/Q189401","display_name":"Virtual memory","level":4,"score":0.08884561061859131},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.06202003359794617},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C46141821","wikidata":"https://www.wikidata.org/wiki/Q209402","display_name":"Nuclear magnetic resonance","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C47701112","wikidata":"https://www.wikidata.org/wiki/Q735188","display_name":"Protein structure","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/hpcsim.2016.7568324","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hpcsim.2016.7568324","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 International Conference on High Performance Computing &amp; Simulation (HPCS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W1973551931","https://openalex.org/W2086551977","https://openalex.org/W2102480715","https://openalex.org/W2102863623","https://openalex.org/W2104528906","https://openalex.org/W2116015411","https://openalex.org/W2116059696","https://openalex.org/W2128072764","https://openalex.org/W2132534681","https://openalex.org/W2133507530","https://openalex.org/W2143068308","https://openalex.org/W2145064068","https://openalex.org/W2152652532","https://openalex.org/W4230988763","https://openalex.org/W4250822204","https://openalex.org/W4253094798","https://openalex.org/W6675837356"],"related_works":["https://openalex.org/W1604898313","https://openalex.org/W2164287667","https://openalex.org/W4233815414","https://openalex.org/W2140418760","https://openalex.org/W1969828050","https://openalex.org/W2908634196","https://openalex.org/W2757974127","https://openalex.org/W2365477072","https://openalex.org/W2051228508","https://openalex.org/W2390310475"],"abstract_inverted_index":{"Chip-level":[0],"Redundant":[1],"Threading":[2],"(CRT)":[3],"is":[4,61,115,129,133,170],"a":[5,42,46,74,93,146,161],"generic":[6],"approach":[7,39],"employed":[8],"in":[9,82,152,156],"multi-core":[10],"architectures":[11],"to":[12,63,122],"meet":[13],"reliability":[14],"or":[15,140],"functional":[16],"safety":[17],"requirements":[18],"of":[19,51,59,69,76,138,149],"applications.":[20],"Critical":[21],"tasks":[22,60,169,175],"are":[23,89,92,108],"concurrently":[24],"executed":[25],"on":[26,45],"several":[27],"processing":[28],"elements":[29,52],"(PEs).":[30],"Most":[31],"approaches":[32],"follow":[33],"the":[34,104,164],"fault":[35],"detection":[36],"and":[37,48,57,95,154,173],"containment":[38],"by":[40],"employing":[41],"Sphere-of-Replication":[43],"(SoR)":[44],"fixed":[47],"hard-wired":[49],"set":[50],"(PEs,":[53],"memory":[54,127,142],"regions).":[55],"Execution":[56],"verification":[58,113],"bounded":[62],"this":[64,83],"SoR":[65],"set.":[66],"The":[67,112,131],"rigidity":[68],"design-time":[70],"chosen":[71,109],"PEs":[72,139],"has":[73,145],"number":[75],"disadvantages.":[77],"To":[78],"enable":[79],"more":[80],"flexibility,":[81],"work":[84],"Flexible":[85],"CRT":[86],"Sets":[87],"(FCRTS)":[88],"used.":[90],"FCRTS":[91],"hardware-based":[94],"run-time":[96],"configurable":[97],"approach.":[98],"Three":[99],"arbitrary":[100],"PEs,":[101],"which":[102],"execute":[103],"same":[105],"task":[106],"set,":[107],"at":[110],"run-time.":[111],"functionality":[114],"implemented":[116],"within":[117],"shared":[118],"components.":[119],"In":[120],"order":[121],"protect":[123],"shared-memory,":[124],"an":[125],"extended":[126],"controller":[128],"introduced.":[130],"method":[132],"architecture":[134],"independent":[135],"i.e.":[136],"choice":[137],"target":[141],"technology.":[143],"It":[144],"small":[147],"footprint":[148],"just":[150],"7.2%":[151],"registers":[153],"6.2%":[155],"LUTs":[157],"when":[158],"synthesized":[159],"for":[160,167],"FPGA.":[162],"Moreover,":[163],"performance":[165,180],"penalty":[166],"critical":[168],"only":[171],"17%":[172],"uncritical":[174],"do":[176],"not":[177],"experience":[178],"any":[179],"degradation.":[181]},"counts_by_year":[{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
