{"id":"https://openalex.org/W1981369369","doi":"https://doi.org/10.1109/hpcsim.2013.6641433","title":"Design of directory based cache coherence protocol verification logic in CMPs around TACA","display_name":"Design of directory based cache coherence protocol verification logic in CMPs around TACA","publication_year":2013,"publication_date":"2013-07-01","ids":{"openalex":"https://openalex.org/W1981369369","doi":"https://doi.org/10.1109/hpcsim.2013.6641433","mag":"1981369369"},"language":"en","primary_location":{"id":"doi:10.1109/hpcsim.2013.6641433","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hpcsim.2013.6641433","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 International Conference on High Performance Computing &amp; Simulation (HPCS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5024913744","display_name":"Mamata Dalui","orcid":"https://orcid.org/0000-0001-5829-541X"},"institutions":[{"id":"https://openalex.org/I155837530","display_name":"National Institute of Technology Durgapur","ror":"https://ror.org/04ds0jm32","country_code":"IN","type":"education","lineage":["https://openalex.org/I155837530"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Mamata Dalui","raw_affiliation_strings":["Department of CSE, National Institute of Technology, Durgapur, West Bengal, India","Dept. of CSE, Nat. Inst. of Technol., Durgapur, India"],"affiliations":[{"raw_affiliation_string":"Department of CSE, National Institute of Technology, Durgapur, West Bengal, India","institution_ids":["https://openalex.org/I155837530"]},{"raw_affiliation_string":"Dept. of CSE, Nat. Inst. of Technol., Durgapur, India","institution_ids":["https://openalex.org/I155837530"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5089134920","display_name":"Biplab K. Sikdar","orcid":"https://orcid.org/0000-0002-9394-8540"},"institutions":[{"id":"https://openalex.org/I98365261","display_name":"Indian Institute of Engineering Science and Technology, Shibpur","ror":"https://ror.org/02ytfzr55","country_code":"IN","type":"education","lineage":["https://openalex.org/I98365261"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Biplab K Sikdar","raw_affiliation_strings":["Department of CST, Bengal Engineering and Science University, West Bengal, India","Dept. of CST, Bengal Eng. & Sci. Univ., Shibpur, India"],"affiliations":[{"raw_affiliation_string":"Department of CST, Bengal Engineering and Science University, West Bengal, India","institution_ids":["https://openalex.org/I98365261"]},{"raw_affiliation_string":"Dept. of CST, Bengal Eng. & Sci. Univ., Shibpur, India","institution_ids":["https://openalex.org/I98365261"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5024913744"],"corresponding_institution_ids":["https://openalex.org/I155837530"],"apc_list":null,"apc_paid":null,"fwci":0.4805,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.67827016,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"318","last_page":"325"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/mesi-protocol","display_name":"MESI protocol","score":0.8288264274597168},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8209496140480042},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.663566529750824},{"id":"https://openalex.org/keywords/directory","display_name":"Directory","score":0.6317944526672363},{"id":"https://openalex.org/keywords/cache-coherence","display_name":"Cache coherence","score":0.5673521757125854},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.5378614664077759},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5005686283111572},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.4479958415031433},{"id":"https://openalex.org/keywords/protocol","display_name":"Protocol (science)","score":0.4185444116592407},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.36636921763420105},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.32175153493881226},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.19581487774848938}],"concepts":[{"id":"https://openalex.org/C120936851","wikidata":"https://www.wikidata.org/wiki/Q1408065","display_name":"MESI protocol","level":5,"score":0.8288264274597168},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8209496140480042},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.663566529750824},{"id":"https://openalex.org/C2777683733","wikidata":"https://www.wikidata.org/wiki/Q201456","display_name":"Directory","level":2,"score":0.6317944526672363},{"id":"https://openalex.org/C141917322","wikidata":"https://www.wikidata.org/wiki/Q1025017","display_name":"Cache coherence","level":5,"score":0.5673521757125854},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.5378614664077759},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5005686283111572},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.4479958415031433},{"id":"https://openalex.org/C2780385302","wikidata":"https://www.wikidata.org/wiki/Q367158","display_name":"Protocol (science)","level":3,"score":0.4185444116592407},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.36636921763420105},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.32175153493881226},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.19581487774848938},{"id":"https://openalex.org/C142724271","wikidata":"https://www.wikidata.org/wiki/Q7208","display_name":"Pathology","level":1,"score":0.0},{"id":"https://openalex.org/C204787440","wikidata":"https://www.wikidata.org/wiki/Q188504","display_name":"Alternative medicine","level":2,"score":0.0},{"id":"https://openalex.org/C71924100","wikidata":"https://www.wikidata.org/wiki/Q11190","display_name":"Medicine","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/hpcsim.2013.6641433","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hpcsim.2013.6641433","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 International Conference on High Performance Computing &amp; Simulation (HPCS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W171399205","https://openalex.org/W1974927049","https://openalex.org/W2003566819","https://openalex.org/W2043569543","https://openalex.org/W2043724035","https://openalex.org/W2052612139","https://openalex.org/W2126603706","https://openalex.org/W2136510033","https://openalex.org/W2146784273","https://openalex.org/W2152074300","https://openalex.org/W2153184575","https://openalex.org/W2166615043","https://openalex.org/W2169213530","https://openalex.org/W2169387321","https://openalex.org/W4205636972","https://openalex.org/W4249165316","https://openalex.org/W6685113883"],"related_works":["https://openalex.org/W2290195868","https://openalex.org/W4285204597","https://openalex.org/W3193874149","https://openalex.org/W2139534474","https://openalex.org/W2013212244","https://openalex.org/W2290179447","https://openalex.org/W2123859627","https://openalex.org/W3139889547","https://openalex.org/W1993010599","https://openalex.org/W2086718556"],"abstract_inverted_index":{"The":[0,76],"conventional":[1],"test":[2,20],"schemes":[3],"for":[4,18,38,99],"Chip":[5],"Multiprocessors":[6],"(CMPs)":[7],"are":[8],"costly,":[9],"time":[10],"consuming":[11],"and":[12],"power":[13],"hungry.":[14],"This":[15],"demands":[16],"search":[17],"new":[19],"methodologies.":[21],"In":[22],"this":[23],"work,":[24],"we":[25],"employ":[26],"cellular":[27,58],"automata":[28,59],"(CA)":[29],"to":[30,52,64,81],"develop":[31],"a":[32],"high":[33],"speed":[34],"protocol":[35],"verification":[36],"logic":[37],"CMPs":[39],"realizing":[40],"directory":[41],"based":[42],"cache":[43,69,94],"coherence":[44],"system.":[45],"A":[46],"special":[47],"class":[48],"of":[49,72,86],"CA":[50],"referred":[51],"as":[53],"single":[54],"length":[55],"cycle":[56],"2-attractor":[57],"(TACA),":[60],"has":[61],"been":[62],"introduced":[63],"identify":[65],"the":[66,87,93,100],"inconsistencies":[67],"in":[68],"line":[70],"states":[71],"processors":[73],"private":[74],"caches.":[75],"TACA":[77],"theory":[78],"is":[79,97],"developed":[80],"realize":[82],"low":[83],"cost":[84],"hardware":[85],"design":[88],"enabling":[89],"quick":[90],"decision":[91],"on":[92],"coherency":[95],"that":[96],"desirable":[98],"CMPs.":[101]},"counts_by_year":[{"year":2026,"cited_by_count":2},{"year":2024,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2026-03-18T14:38:29.013473","created_date":"2025-10-10T00:00:00"}
