{"id":"https://openalex.org/W2148466748","doi":"https://doi.org/10.1109/hpcsim.2011.5999874","title":"Creating HW/SW co-designed MPSoPC's from high level programming models","display_name":"Creating HW/SW co-designed MPSoPC's from high level programming models","publication_year":2011,"publication_date":"2011-07-01","ids":{"openalex":"https://openalex.org/W2148466748","doi":"https://doi.org/10.1109/hpcsim.2011.5999874","mag":"2148466748"},"language":"en","primary_location":{"id":"doi:10.1109/hpcsim.2011.5999874","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hpcsim.2011.5999874","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 International Conference on High Performance Computing &amp; Simulation","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5042096109","display_name":"Eugene Cartwright","orcid":null},"institutions":[{"id":"https://openalex.org/I78715868","display_name":"University of Arkansas at Fayetteville","ror":"https://ror.org/05jbt9m15","country_code":"US","type":"education","lineage":["https://openalex.org/I78715868"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Eugene Cartwright","raw_affiliation_strings":["Computer Science & Computer Engineering Department, University of Arkansas, USA"],"affiliations":[{"raw_affiliation_string":"Computer Science & Computer Engineering Department, University of Arkansas, USA","institution_ids":["https://openalex.org/I78715868"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5076736040","display_name":"Sen Ma","orcid":"https://orcid.org/0000-0001-7363-0845"},"institutions":[{"id":"https://openalex.org/I78715868","display_name":"University of Arkansas at Fayetteville","ror":"https://ror.org/05jbt9m15","country_code":"US","type":"education","lineage":["https://openalex.org/I78715868"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sen Ma","raw_affiliation_strings":["Computer Science & Computer Engineering Department, University of Arkansas, USA"],"affiliations":[{"raw_affiliation_string":"Computer Science & Computer Engineering Department, University of Arkansas, USA","institution_ids":["https://openalex.org/I78715868"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5062434121","display_name":"David Andrews","orcid":"https://orcid.org/0000-0003-1464-7107"},"institutions":[{"id":"https://openalex.org/I78715868","display_name":"University of Arkansas at Fayetteville","ror":"https://ror.org/05jbt9m15","country_code":"US","type":"education","lineage":["https://openalex.org/I78715868"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"David Andrews","raw_affiliation_strings":["Computer Science & Computer Engineering Department, University of Arkansas, USA"],"affiliations":[{"raw_affiliation_string":"Computer Science & Computer Engineering Department, University of Arkansas, USA","institution_ids":["https://openalex.org/I78715868"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5069173833","display_name":"Miaoqing Huang","orcid":"https://orcid.org/0000-0001-7376-3744"},"institutions":[{"id":"https://openalex.org/I78715868","display_name":"University of Arkansas at Fayetteville","ror":"https://ror.org/05jbt9m15","country_code":"US","type":"education","lineage":["https://openalex.org/I78715868"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Miaoqing Huang","raw_affiliation_strings":["Computer Science & Computer Engineering Department, University of Arkansas, USA"],"affiliations":[{"raw_affiliation_string":"Computer Science & Computer Engineering Department, University of Arkansas, USA","institution_ids":["https://openalex.org/I78715868"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5042096109"],"corresponding_institution_ids":["https://openalex.org/I78715868"],"apc_list":null,"apc_paid":null,"fwci":1.2592,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.81911035,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"45","issue":null,"first_page":"554","last_page":"560"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/mpsoc","display_name":"MPSoC","score":0.8385038375854492},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8277450799942017},{"id":"https://openalex.org/keywords/microkernel","display_name":"Microkernel","score":0.7805677652359009},{"id":"https://openalex.org/keywords/multiprocessing","display_name":"Multiprocessing","score":0.7370359897613525},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6631506085395813},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6171084642410278},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.5185133218765259},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5167090892791748},{"id":"https://openalex.org/keywords/posix-threads","display_name":"POSIX Threads","score":0.4827636778354645},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.47474414110183716},{"id":"https://openalex.org/keywords/programming-paradigm","display_name":"Programming paradigm","score":0.4548736810684204},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.422770619392395},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.4218299686908722},{"id":"https://openalex.org/keywords/thread","display_name":"Thread (computing)","score":0.13808223605155945},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.10520729422569275}],"concepts":[{"id":"https://openalex.org/C2777187653","wikidata":"https://www.wikidata.org/wiki/Q975106","display_name":"MPSoC","level":3,"score":0.8385038375854492},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8277450799942017},{"id":"https://openalex.org/C2777127024","wikidata":"https://www.wikidata.org/wiki/Q726378","display_name":"Microkernel","level":2,"score":0.7805677652359009},{"id":"https://openalex.org/C4822641","wikidata":"https://www.wikidata.org/wiki/Q846651","display_name":"Multiprocessing","level":2,"score":0.7370359897613525},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6631506085395813},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6171084642410278},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.5185133218765259},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5167090892791748},{"id":"https://openalex.org/C41138395","wikidata":"https://www.wikidata.org/wiki/Q928112","display_name":"POSIX Threads","level":3,"score":0.4827636778354645},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.47474414110183716},{"id":"https://openalex.org/C34165917","wikidata":"https://www.wikidata.org/wiki/Q188267","display_name":"Programming paradigm","level":2,"score":0.4548736810684204},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.422770619392395},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.4218299686908722},{"id":"https://openalex.org/C138101251","wikidata":"https://www.wikidata.org/wiki/Q213092","display_name":"Thread (computing)","level":2,"score":0.13808223605155945},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.10520729422569275}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/hpcsim.2011.5999874","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hpcsim.2011.5999874","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 International Conference on High Performance Computing &amp; Simulation","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W1923325560","https://openalex.org/W1974394055","https://openalex.org/W1983719724","https://openalex.org/W1988888548","https://openalex.org/W1993168130","https://openalex.org/W2080393180","https://openalex.org/W2097959379","https://openalex.org/W2121758805","https://openalex.org/W2123264781","https://openalex.org/W2149777400","https://openalex.org/W2151994818","https://openalex.org/W2154716491","https://openalex.org/W2160955218","https://openalex.org/W3150407198","https://openalex.org/W4249437221","https://openalex.org/W6648682248","https://openalex.org/W6678583733"],"related_works":["https://openalex.org/W11413300","https://openalex.org/W1976012348","https://openalex.org/W2614713859","https://openalex.org/W2002682434","https://openalex.org/W4387782849","https://openalex.org/W2137671689","https://openalex.org/W2012131147","https://openalex.org/W2113449380","https://openalex.org/W3146394219","https://openalex.org/W2157008728"],"abstract_inverted_index":{"FPGA":[0,23],"densities":[1],"have":[2],"continued":[3],"to":[4,27,61,99,122,129],"follow":[5],"Moore's":[6],"law":[7],"and":[8,39,90,97],"can":[9],"now":[10],"support":[11],"a":[12,29,55,66,102,124],"complete":[13,67],"multiprocessor":[14,70,106],"system":[15,32,71,107,128],"on":[16,72,108],"programmable":[17,73],"chip.":[18],"The":[19],"benefits":[20],"of":[21,34,47,65],"the":[22,25,45,63,137],"include":[24],"ability":[26],"build":[28],"customized":[30],"MPSoC":[31],"consisting":[33],"heterogeneous":[35],"processing":[36],"resources,":[37],"interconnects":[38],"memory":[40,105],"hierarchies":[41],"that":[42,58],"best":[43],"match":[44],"requirements":[46],"each":[48],"application.":[49],"In":[50],"this":[51],"paper":[52],"we":[53],"outline":[54],"new":[56],"approach":[57],"allows":[59],"users":[60],"drive":[62],"generation":[64],"hardware/software":[68],"co-designed":[69],"chip":[74,109],"from":[75],"an":[76],"unaltered":[77],"standard":[78],"high":[79],"level":[80],"programming":[81],"model.":[82],"We":[83,114],"use":[84],"OpenCL":[85,117],"as":[86],"our":[87],"specification":[88],"framework":[89],"show":[91,115],"how":[92,116],"key":[93],"API's":[94,118],"are":[95,119],"extracted":[96],"used":[98],"automatically":[100],"create":[101],"distributed":[103],"shared":[104],"architecture":[110],"for":[111],"Xilinx":[112],"FPGA's.":[113],"easily":[120],"translated":[121],"hthreads,":[123],"hardware-based":[125],"microkernel":[126],"operating":[127],"provide":[130],"pthreads":[131],"compliant":[132],"run":[133],"time":[134],"services":[135],"within":[136],"MPSoPC":[138],"architecture.":[139]},"counts_by_year":[{"year":2020,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":2},{"year":2012,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
