{"id":"https://openalex.org/W3084294953","doi":"https://doi.org/10.1109/hpcs48598.2019.9188201","title":"New CAD Tools to ConFigure Tree-Based Embedded FPGA","display_name":"New CAD Tools to ConFigure Tree-Based Embedded FPGA","publication_year":2019,"publication_date":"2019-07-01","ids":{"openalex":"https://openalex.org/W3084294953","doi":"https://doi.org/10.1109/hpcs48598.2019.9188201","mag":"3084294953"},"language":"en","primary_location":{"id":"doi:10.1109/hpcs48598.2019.9188201","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hpcs48598.2019.9188201","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 International Conference on High Performance Computing &amp; Simulation (HPCS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5007944276","display_name":"Hajer Saidi","orcid":"https://orcid.org/0000-0002-6408-4843"},"institutions":[{"id":"https://openalex.org/I4210119561","display_name":"Digital Research Centre of Sfax","ror":"https://ror.org/02s48dm85","country_code":"TN","type":"facility","lineage":["https://openalex.org/I4210119561"]}],"countries":["TN"],"is_corresponding":true,"raw_author_name":"H. Saidi","raw_affiliation_strings":["CES Research Laboratory, National Engineering School of Sfax Digital Research center of Sfax (CRNS), Sfax, Sfax, Tunisia"],"affiliations":[{"raw_affiliation_string":"CES Research Laboratory, National Engineering School of Sfax Digital Research center of Sfax (CRNS), Sfax, Sfax, Tunisia","institution_ids":["https://openalex.org/I4210119561"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5019168974","display_name":"Mariem Turki","orcid":"https://orcid.org/0000-0003-2646-3962"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"M. Turki","raw_affiliation_strings":["CES Research Laboratory, National Engineering School of Sfax, Sfax, Tunisia"],"affiliations":[{"raw_affiliation_string":"CES Research Laboratory, National Engineering School of Sfax, Sfax, Tunisia","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111979965","display_name":"Z. Marrakchi","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Z. Marrakchi","raw_affiliation_strings":["Mentor Graphics, Tunisia"],"affiliations":[{"raw_affiliation_string":"Mentor Graphics, Tunisia","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5020813947","display_name":"Mohammed S. Saleh","orcid":"https://orcid.org/0000-0002-5396-102X"},"institutions":[{"id":"https://openalex.org/I1284598098","display_name":"King Abdulaziz City for Science and Technology","ror":"https://ror.org/05tdz6m39","country_code":"SA","type":"facility","lineage":["https://openalex.org/I1284598098"]}],"countries":["SA"],"is_corresponding":false,"raw_author_name":"M. S. Ben Saleh","raw_affiliation_strings":["National Electronics and Photonics Technology Center, King Abdulaziz City for Science and Technology, Riyadh, Riyadh, Saudi Arabia"],"affiliations":[{"raw_affiliation_string":"National Electronics and Photonics Technology Center, King Abdulaziz City for Science and Technology, Riyadh, Riyadh, Saudi Arabia","institution_ids":["https://openalex.org/I1284598098"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5112780554","display_name":"Mohamed Abid","orcid":"https://orcid.org/0009-0005-2082-3287"},"institutions":[{"id":"https://openalex.org/I4210119561","display_name":"Digital Research Centre of Sfax","ror":"https://ror.org/02s48dm85","country_code":"TN","type":"facility","lineage":["https://openalex.org/I4210119561"]}],"countries":["TN"],"is_corresponding":false,"raw_author_name":"M. Abid","raw_affiliation_strings":["CES Research Laboratory, National Engineering School of Sfax Digital Research center of Sfax (CRNS), Sfax, Sfax, Tunisia"],"affiliations":[{"raw_affiliation_string":"CES Research Laboratory, National Engineering School of Sfax Digital Research center of Sfax (CRNS), Sfax, Sfax, Tunisia","institution_ids":["https://openalex.org/I4210119561"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5007944276"],"corresponding_institution_ids":["https://openalex.org/I4210119561"],"apc_list":null,"apc_paid":null,"fwci":0.4769,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.67083472,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":95},"biblio":{"volume":"7","issue":null,"first_page":"643","last_page":"649"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8623471260070801},{"id":"https://openalex.org/keywords/reconfigurability","display_name":"Reconfigurability","score":0.8475462198257446},{"id":"https://openalex.org/keywords/workflow","display_name":"Workflow","score":0.771891713142395},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7618561387062073},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6421015858650208},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.5942426919937134},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5847019553184509},{"id":"https://openalex.org/keywords/fpga-prototype","display_name":"FPGA prototype","score":0.547120988368988},{"id":"https://openalex.org/keywords/flexibility","display_name":"Flexibility (engineering)","score":0.48905977606773376},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.2536264657974243},{"id":"https://openalex.org/keywords/database","display_name":"Database","score":0.08767625689506531}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8623471260070801},{"id":"https://openalex.org/C2780149590","wikidata":"https://www.wikidata.org/wiki/Q7302742","display_name":"Reconfigurability","level":2,"score":0.8475462198257446},{"id":"https://openalex.org/C177212765","wikidata":"https://www.wikidata.org/wiki/Q627335","display_name":"Workflow","level":2,"score":0.771891713142395},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7618561387062073},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6421015858650208},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.5942426919937134},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5847019553184509},{"id":"https://openalex.org/C203864433","wikidata":"https://www.wikidata.org/wiki/Q5426992","display_name":"FPGA prototype","level":3,"score":0.547120988368988},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.48905977606773376},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.2536264657974243},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.08767625689506531},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/hpcs48598.2019.9188201","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hpcs48598.2019.9188201","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 International Conference on High Performance Computing &amp; Simulation (HPCS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.4300000071525574}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W128300022","https://openalex.org/W144683508","https://openalex.org/W1484050268","https://openalex.org/W1528837436","https://openalex.org/W1543351822","https://openalex.org/W1591851732","https://openalex.org/W2029541370","https://openalex.org/W2060454511","https://openalex.org/W2079454012","https://openalex.org/W2109220922","https://openalex.org/W2111756578","https://openalex.org/W2148243454","https://openalex.org/W2154900953","https://openalex.org/W2168493238","https://openalex.org/W2583923580","https://openalex.org/W2769830722","https://openalex.org/W4241806018","https://openalex.org/W4392496337","https://openalex.org/W6605142654","https://openalex.org/W6862381607"],"related_works":["https://openalex.org/W2159103767","https://openalex.org/W2998132311","https://openalex.org/W2207067480","https://openalex.org/W4383823603","https://openalex.org/W2332075903","https://openalex.org/W1579891439","https://openalex.org/W2291257309","https://openalex.org/W2082487009","https://openalex.org/W272033699","https://openalex.org/W1692883217"],"abstract_inverted_index":{"An":[0],"embedded":[1],"FPGA":[2,40],"(e-FPGA)":[3],"is":[4,103,118],"an":[5,86,107],"IP":[6],"which":[7],"can":[8],"be":[9,30],"integrated":[10],"in":[11],"a":[12,38,47],"System":[13],"on":[14],"Chip":[15],"architecture":[16],"to":[17,23,29,37,50,73,92,112,120,127],"add":[18],"more":[19],"flexibility":[20],"and":[21,33,69],"reconfigurability":[22],"the":[24,74,82,93,113,121,124,129,133,137],"design.":[25],"This":[26,116],"e-FPGA":[27,53,76,101],"needs":[28],"designed,":[31],"optimized":[32],"configured":[34],"differently":[35],"compared":[36,91,111],"classic":[39],"chip.":[41],"In":[42],"this":[43],"paper,":[44],"we":[45],"propose":[46],"full":[48],"workflow":[49,56,80,95,135],"conFigure":[51],"tree-based":[52,138],"architecture.":[54,64,99,115,139],"The":[55,78,100],"includes":[57],"some":[58],"existing":[59],"tools":[60,68,126],"used":[61,96],"for":[62,97,136],"mesh":[63,98,114],"We":[65],"modified":[66],"these":[67],"adapt":[70],"them":[71],"accordingly":[72],"proposed":[75],"constraints.":[77],"new":[79],"reduces":[81],"execution":[83],"runtime":[84],"by":[85,106],"average":[87,108],"of":[88,109,123,132],"57":[89],"%":[90],"academic":[94],"area":[102],"also":[104],"reduced":[105],"27%":[110],"optimization":[117],"due":[119],"ability":[122],"CAD":[125],"manage":[128],"different":[130],"processes":[131],"configuration":[134]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
