{"id":"https://openalex.org/W3083838449","doi":"https://doi.org/10.1109/hpcs48598.2019.9188138","title":"Exploration of Clustering Algorithms effects on Mesh of Clusters based FPGA Architecture Performance","display_name":"Exploration of Clustering Algorithms effects on Mesh of Clusters based FPGA Architecture Performance","publication_year":2019,"publication_date":"2019-07-01","ids":{"openalex":"https://openalex.org/W3083838449","doi":"https://doi.org/10.1109/hpcs48598.2019.9188138","mag":"3083838449"},"language":"en","primary_location":{"id":"doi:10.1109/hpcs48598.2019.9188138","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hpcs48598.2019.9188138","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 International Conference on High Performance Computing & Simulation (HPCS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5049692974","display_name":"Khouloud Bouaziz","orcid":"https://orcid.org/0000-0003-0770-1419"},"institutions":[{"id":"https://openalex.org/I142899784","display_name":"University of Sfax","ror":"https://ror.org/04d4sd432","country_code":"TN","type":"education","lineage":["https://openalex.org/I142899784"]}],"countries":["TN"],"is_corresponding":true,"raw_author_name":"Khouloud Bouaziz","raw_affiliation_strings":["CES Laboratory, National School of Engineers of Sfax, University of Sfax, Sfax, Tunisia"],"affiliations":[{"raw_affiliation_string":"CES Laboratory, National School of Engineers of Sfax, University of Sfax, Sfax, Tunisia","institution_ids":["https://openalex.org/I142899784"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5024841287","display_name":"Sonda Chtourou","orcid":"https://orcid.org/0000-0001-5669-242X"},"institutions":[{"id":"https://openalex.org/I142899784","display_name":"University of Sfax","ror":"https://ror.org/04d4sd432","country_code":"TN","type":"education","lineage":["https://openalex.org/I142899784"]}],"countries":["TN"],"is_corresponding":false,"raw_author_name":"Sonda Chtourou","raw_affiliation_strings":["CES Laboratory, National School of Engineers of Sfax, University of Sfax, Sfax, Tunisia"],"affiliations":[{"raw_affiliation_string":"CES Laboratory, National School of Engineers of Sfax, University of Sfax, Sfax, Tunisia","institution_ids":["https://openalex.org/I142899784"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111822030","display_name":"Zied Marrakchi","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Zied Marrakchi","raw_affiliation_strings":["Mentor Graphics, Tunis, Tunisia"],"affiliations":[{"raw_affiliation_string":"Mentor Graphics, Tunis, Tunisia","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5026522015","display_name":"Mohamed Abid","orcid":"https://orcid.org/0000-0001-7409-292X"},"institutions":[{"id":"https://openalex.org/I142899784","display_name":"University of Sfax","ror":"https://ror.org/04d4sd432","country_code":"TN","type":"education","lineage":["https://openalex.org/I142899784"]}],"countries":["TN"],"is_corresponding":false,"raw_author_name":"Mohamed Abid","raw_affiliation_strings":["CES Laboratory, National School of Engineers of Sfax, University of Sfax, Sfax, Tunisia"],"affiliations":[{"raw_affiliation_string":"CES Laboratory, National School of Engineers of Sfax, University of Sfax, Sfax, Tunisia","institution_ids":["https://openalex.org/I142899784"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5109086263","display_name":"Abdulfattah M. Obeid","orcid":null},"institutions":[{"id":"https://openalex.org/I1284598098","display_name":"King Abdulaziz City for Science and Technology","ror":"https://ror.org/05tdz6m39","country_code":"SA","type":"facility","lineage":["https://openalex.org/I1284598098"]}],"countries":["SA"],"is_corresponding":false,"raw_author_name":"Abdulfattah Obeid","raw_affiliation_strings":["National Center for Electronics and Photonics Technology, KACST, Riyadh, Saudi Arabia"],"affiliations":[{"raw_affiliation_string":"National Center for Electronics and Photonics Technology, KACST, Riyadh, Saudi Arabia","institution_ids":["https://openalex.org/I1284598098"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5049692974"],"corresponding_institution_ids":["https://openalex.org/I142899784"],"apc_list":null,"apc_paid":null,"fwci":0.2385,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.58253919,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":93,"max":95},"biblio":{"volume":"497","issue":null,"first_page":"658","last_page":"665"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8815540075302124},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7742111682891846},{"id":"https://openalex.org/keywords/cluster-analysis","display_name":"Cluster analysis","score":0.739503800868988},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.5827333927154541},{"id":"https://openalex.org/keywords/critical-path-method","display_name":"Critical path method","score":0.5321207642555237},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4757796823978424},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.45657801628112793},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4388575255870819},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.4036109447479248},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.38172250986099243},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.36853307485580444},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3588830232620239},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.13990601897239685},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1270807683467865}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8815540075302124},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7742111682891846},{"id":"https://openalex.org/C73555534","wikidata":"https://www.wikidata.org/wiki/Q622825","display_name":"Cluster analysis","level":2,"score":0.739503800868988},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.5827333927154541},{"id":"https://openalex.org/C115874739","wikidata":"https://www.wikidata.org/wiki/Q825377","display_name":"Critical path method","level":2,"score":0.5321207642555237},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4757796823978424},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.45657801628112793},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4388575255870819},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4036109447479248},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.38172250986099243},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.36853307485580444},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3588830232620239},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.13990601897239685},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1270807683467865},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/hpcs48598.2019.9188138","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hpcs48598.2019.9188138","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 International Conference on High Performance Computing & Simulation (HPCS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8700000047683716,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":33,"referenced_works":["https://openalex.org/W831895150","https://openalex.org/W1518236483","https://openalex.org/W1523051745","https://openalex.org/W1967128905","https://openalex.org/W1977850862","https://openalex.org/W2002641171","https://openalex.org/W2033685698","https://openalex.org/W2047199967","https://openalex.org/W2055251702","https://openalex.org/W2077892593","https://openalex.org/W2078174680","https://openalex.org/W2083637347","https://openalex.org/W2095431940","https://openalex.org/W2111756578","https://openalex.org/W2113645429","https://openalex.org/W2122724240","https://openalex.org/W2128473621","https://openalex.org/W2137454730","https://openalex.org/W2149513075","https://openalex.org/W2150281391","https://openalex.org/W2151614223","https://openalex.org/W2157761128","https://openalex.org/W2168493238","https://openalex.org/W2275304190","https://openalex.org/W2293079373","https://openalex.org/W2755766879","https://openalex.org/W2904375987","https://openalex.org/W3023858524","https://openalex.org/W4246219036","https://openalex.org/W4246961877","https://openalex.org/W4252890894","https://openalex.org/W6682237558","https://openalex.org/W7068219351"],"related_works":["https://openalex.org/W2098419840","https://openalex.org/W1966764473","https://openalex.org/W2789349722","https://openalex.org/W1985308002","https://openalex.org/W2121963733","https://openalex.org/W1977171228","https://openalex.org/W2059422871","https://openalex.org/W2766377030","https://openalex.org/W2041787842","https://openalex.org/W2170504327"],"abstract_inverted_index":{"Field":[0],"Programmable":[1],"Gate":[2],"Arrays":[3],"(FPGAs)":[4],"have":[5],"become":[6],"a":[7,22],"popular":[8],"medium":[9],"for":[10,146],"the":[11,43,72,93],"implementation":[12,41],"of":[13,24,39,47,65,95,136],"many":[14],"digital":[15],"circuits.":[16],"Mapping":[17],"applications":[18],"into":[19],"FPGAs":[20],"requires":[21],"set":[23],"efficient":[25],"Computer-Aided":[26],"Design":[27],"(CAD)":[28],"tools":[29],"to":[30,62,144],"obtain":[31],"high-quality":[32],"Integrated":[33],"Circuits":[34],"(ICs).":[35],"One":[36],"critical":[37,128],"issue":[38],"FPGA":[40,68,80,106],"is":[42],"quality":[44],"and":[45,102,117,131,140],"efficiency":[46],"associated":[48],"CAD":[49],"algorithms.":[50],"In":[51,70,88],"this":[52,89],"paper,":[53,90],"we":[54,74,91],"are":[55],"interested":[56],"in":[57],"investigating":[58],"clustering":[59,97,122],"algorithms":[60,98],"aspect":[61],"optimize":[63],"Mesh":[64],"Clusters":[66],"(MoCs)":[67],"performance.":[69,87],"fact,":[71],"way":[73],"distribute":[75],"Logic":[76],"Blocks":[77],"(LBs)":[78],"between":[79],"clusters":[81],"has":[82],"an":[83,134],"important":[84],"impact":[85],"on":[86,104,110],"explore":[92],"effects":[94],"two":[96],"(First":[99],"Choice":[100],"(FC)":[101],"T-VPack)":[103],"MoCs":[105,147],"architecture":[107],"based":[108],"only":[109],"short":[111],"routing":[112],"wires.":[113],"This":[114],"paper":[115],"highlights":[116],"experimentally":[118],"demonstrates":[119],"that":[120],"FC":[121],"algorithm":[123],"ameliorates":[124],"power":[125],"consumption,":[126],"area,":[127],"path":[129],"delay":[130],"energy":[132],"by":[133],"average":[135],"17%,":[137],"11%,":[138],"13%":[139],"24%":[141],"respectively":[142],"compared":[143],"T-VPack":[145],"FPGA.":[148]},"counts_by_year":[{"year":2021,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}