{"id":"https://openalex.org/W2333406110","doi":"https://doi.org/10.1109/hpca.2016.7446073","title":"Efficient synthetic traffic models for large, complex SoCs","display_name":"Efficient synthetic traffic models for large, complex SoCs","publication_year":2016,"publication_date":"2016-03-01","ids":{"openalex":"https://openalex.org/W2333406110","doi":"https://doi.org/10.1109/hpca.2016.7446073","mag":"2333406110"},"language":"en","primary_location":{"id":"doi:10.1109/hpca.2016.7446073","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hpca.2016.7446073","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE International Symposium on High Performance Computer Architecture (HPCA)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5082725592","display_name":"Jieming Yin","orcid":"https://orcid.org/0009-0008-2878-1853"},"institutions":[{"id":"https://openalex.org/I1311921367","display_name":"Advanced Micro Devices (Canada)","ror":"https://ror.org/02yh0k313","country_code":"CA","type":"company","lineage":["https://openalex.org/I1311921367","https://openalex.org/I4210137977"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"Jieming Yin","raw_affiliation_strings":["Advanced Micro Devices, Inc"],"affiliations":[{"raw_affiliation_string":"Advanced Micro Devices, Inc","institution_ids":["https://openalex.org/I1311921367"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5064126781","display_name":"Onur Kay\u0131ran","orcid":"https://orcid.org/0009-0006-4482-3115"},"institutions":[{"id":"https://openalex.org/I1311921367","display_name":"Advanced Micro Devices (Canada)","ror":"https://ror.org/02yh0k313","country_code":"CA","type":"company","lineage":["https://openalex.org/I1311921367","https://openalex.org/I4210137977"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Onur Kayiran","raw_affiliation_strings":["Advanced Micro Devices, Inc"],"affiliations":[{"raw_affiliation_string":"Advanced Micro Devices, Inc","institution_ids":["https://openalex.org/I1311921367"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5042040286","display_name":"Matthew Poremba","orcid":"https://orcid.org/0000-0001-9399-9682"},"institutions":[{"id":"https://openalex.org/I1311921367","display_name":"Advanced Micro Devices (Canada)","ror":"https://ror.org/02yh0k313","country_code":"CA","type":"company","lineage":["https://openalex.org/I1311921367","https://openalex.org/I4210137977"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Matthew Poremba","raw_affiliation_strings":["Advanced Micro Devices, Inc"],"affiliations":[{"raw_affiliation_string":"Advanced Micro Devices, Inc","institution_ids":["https://openalex.org/I1311921367"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5060103552","display_name":"Natalie Enright Jerger","orcid":"https://orcid.org/0000-0002-0526-2080"},"institutions":[{"id":"https://openalex.org/I1311921367","display_name":"Advanced Micro Devices (Canada)","ror":"https://ror.org/02yh0k313","country_code":"CA","type":"company","lineage":["https://openalex.org/I1311921367","https://openalex.org/I4210137977"]},{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Natalie Enright Jerger","raw_affiliation_strings":["Advanced Micro Devices, Inc","University of Toronto"],"affiliations":[{"raw_affiliation_string":"Advanced Micro Devices, Inc","institution_ids":["https://openalex.org/I1311921367"]},{"raw_affiliation_string":"University of Toronto","institution_ids":["https://openalex.org/I185261750"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5102835155","display_name":"Gabriel H. Loh","orcid":"https://orcid.org/0000-0002-4616-0144"},"institutions":[{"id":"https://openalex.org/I1311921367","display_name":"Advanced Micro Devices (Canada)","ror":"https://ror.org/02yh0k313","country_code":"CA","type":"company","lineage":["https://openalex.org/I1311921367","https://openalex.org/I4210137977"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Gabriel H. Loh","raw_affiliation_strings":["Advanced Micro Devices, Inc"],"affiliations":[{"raw_affiliation_string":"Advanced Micro Devices, Inc","institution_ids":["https://openalex.org/I1311921367"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5082725592"],"corresponding_institution_ids":["https://openalex.org/I1311921367"],"apc_list":null,"apc_paid":null,"fwci":1.79121105,"has_fulltext":false,"cited_by_count":13,"citation_normalized_percentile":{"value":0.86747199,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"297","last_page":"308"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9955000281333923,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8684618473052979},{"id":"https://openalex.org/keywords/memory-hierarchy","display_name":"Memory hierarchy","score":0.5578848123550415},{"id":"https://openalex.org/keywords/cache-coherence","display_name":"Cache coherence","score":0.5392064452171326},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.45223256945610046},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.43329381942749023},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.42732134461402893},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.38646674156188965},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3760315477848053},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.36576658487319946},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.35862216353416443},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.28982043266296387}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8684618473052979},{"id":"https://openalex.org/C2778100165","wikidata":"https://www.wikidata.org/wiki/Q1589327","display_name":"Memory hierarchy","level":3,"score":0.5578848123550415},{"id":"https://openalex.org/C141917322","wikidata":"https://www.wikidata.org/wiki/Q1025017","display_name":"Cache coherence","level":5,"score":0.5392064452171326},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.45223256945610046},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.43329381942749023},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.42732134461402893},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.38646674156188965},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3760315477848053},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.36576658487319946},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.35862216353416443},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.28982043266296387}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/hpca.2016.7446073","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hpca.2016.7446073","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE International Symposium on High Performance Computer Architecture (HPCA)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":37,"referenced_works":["https://openalex.org/W1815597787","https://openalex.org/W1941458583","https://openalex.org/W1979527452","https://openalex.org/W1980891674","https://openalex.org/W1985818188","https://openalex.org/W1994999558","https://openalex.org/W2014555481","https://openalex.org/W2022977427","https://openalex.org/W2034861439","https://openalex.org/W2035286849","https://openalex.org/W2067156456","https://openalex.org/W2067354926","https://openalex.org/W2074833769","https://openalex.org/W2078994750","https://openalex.org/W2079751107","https://openalex.org/W2080592089","https://openalex.org/W2103742924","https://openalex.org/W2106562406","https://openalex.org/W2109814389","https://openalex.org/W2118231264","https://openalex.org/W2122900653","https://openalex.org/W2128966690","https://openalex.org/W2139984346","https://openalex.org/W2149257735","https://openalex.org/W2152923781","https://openalex.org/W2157225945","https://openalex.org/W2158924248","https://openalex.org/W2162639668","https://openalex.org/W2166151045","https://openalex.org/W2495393536","https://openalex.org/W2539193928","https://openalex.org/W2546309369","https://openalex.org/W4233332459","https://openalex.org/W4236302577","https://openalex.org/W4237047828","https://openalex.org/W6675771560","https://openalex.org/W6723488237"],"related_works":["https://openalex.org/W3017188964","https://openalex.org/W2549803267","https://openalex.org/W2497617944","https://openalex.org/W2167303720","https://openalex.org/W1563139915","https://openalex.org/W2061075966","https://openalex.org/W3147501184","https://openalex.org/W4256652509","https://openalex.org/W2109715593","https://openalex.org/W2081416538"],"abstract_inverted_index":{"The":[0,260],"interconnect":[1],"or":[2],"network":[3],"on":[4,64,126,199],"chip":[5,128],"(NoC)":[6],"is":[7,75,197,262],"an":[8,200],"increasingly":[9,33],"important":[10,34],"component":[11],"in":[12,18,138],"processors.":[13],"As":[14],"systems":[15],"scale":[16],"up":[17],"size":[19],"and":[20,28,38,82,132,150,165,168,254],"functionality,":[21],"the":[22,36,46,68,73,79,91,110,119,134,139,180,193,251,258],"ability":[23],"to":[24,35,58,78,114,175,208,218,222,225,239],"efficiently":[25],"model":[26,186,209,226,238],"larger":[27,210,228],"more":[29,123,153,247],"complex":[30,124,154],"NoCs":[31],"becomes":[32],"design":[37],"evaluation":[39,249],"of":[40,53,121,136,141,145,250],"such":[41,227],"systems.":[42,212,229],"Recent":[43],"work":[44,94],"proposed":[45],"\"SynFull\"":[47],"methodology":[48,113,183,267],"that":[49,268],"performs":[50],"statistical":[51],"analysis":[52,196,221],"a":[54,101,122,127,142,146,152,187,233,263],"workload's":[55],"NoC":[56,88,120,188,265],"traffic":[57,61,74],"create":[59],"compact":[60],"generators":[62],"based":[63],"Markov":[65],"models.":[66],"While":[67],"models":[69],"generate":[70],"synthetic":[71,235],"traffic,":[72],"statistically":[76],"similar":[77],"original":[80,92,111,181,194],"trace":[81],"can":[83,184],"be":[84,115,223],"used":[85],"for":[86,159,270],"fast":[87],"simulation.":[89],"However,":[90],"SynFull":[93,112,137,182],"only":[95,185],"evaluated":[96],"multi-core":[97],"CPU":[98],"scenarios":[99],"with":[100,189,257],"very":[102],"simple":[103],"cache":[104,155],"coherence":[105,161],"protocol":[106],"(MESI).":[107],"We":[108,130,171],"find":[109],"insufficient":[116],"when":[117,192],"modeling":[118],"system":[125],"(SoC).":[129],"identify":[131],"analyze":[133],"shortcomings":[135],"context":[140],"SoC":[143,273],"consisting":[144],"heterogeneous":[147,169,272],"architecture":[148],"(CPU":[149],"GPU),":[151],"hierarchy":[156],"including":[157],"support":[158],"full":[160],"between":[162],"CPU,":[163],"GPU,":[164],"shared":[166],"caches,":[167],"workloads.":[170],"introduce":[172,215],"new":[173,216],"techniques":[174,217],"address":[176],"these":[177],"shortcomings.":[178],"Furthermore,":[179],"N":[190],"nodes":[191],"application":[195],"performed":[198],"identically-sized":[201],"N-node":[202],"system,":[203],"but":[204],"one":[205],"typically":[206],"wants":[207],"future":[211],"Therefore,":[213],"we":[214,231],"enable":[219],"SynFull-like":[220],"extrapolated":[224],"Finally,":[230],"present":[232],"novel":[234],"memory":[236,252],"reference":[237],"replace":[240],"SynFull's":[241],"fixed":[242],"latency":[243],"model;":[244],"this":[245],"allows":[246],"realistic":[248],"subsystem":[253],"its":[255],"interaction":[256],"NoC.":[259],"result":[261],"robust":[264],"simulation":[266],"works":[269],"large,":[271],"architectures.":[274]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2022,"cited_by_count":3},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}