{"id":"https://openalex.org/W2013028205","doi":"https://doi.org/10.1109/hpca.2015.7056056","title":"Overcoming the challenges of crossbar resistive memory architectures","display_name":"Overcoming the challenges of crossbar resistive memory architectures","publication_year":2015,"publication_date":"2015-02-01","ids":{"openalex":"https://openalex.org/W2013028205","doi":"https://doi.org/10.1109/hpca.2015.7056056","mag":"2013028205"},"language":"en","primary_location":{"id":"doi:10.1109/hpca.2015.7056056","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hpca.2015.7056056","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101777595","display_name":"Cong Xu","orcid":"https://orcid.org/0000-0002-9278-1363"},"institutions":[{"id":"https://openalex.org/I130769515","display_name":"Pennsylvania State University","ror":"https://ror.org/04p491231","country_code":"US","type":"education","lineage":["https://openalex.org/I130769515"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Cong Xu","raw_affiliation_strings":["Pennsylvania State University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Pennsylvania State University","institution_ids":["https://openalex.org/I130769515"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5068606980","display_name":"Dimin Niu","orcid":"https://orcid.org/0000-0001-8440-3875"},"institutions":[{"id":"https://openalex.org/I130769515","display_name":"Pennsylvania State University","ror":"https://ror.org/04p491231","country_code":"US","type":"education","lineage":["https://openalex.org/I130769515"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Dimin Niu","raw_affiliation_strings":["Pennsylvania State University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Pennsylvania State University","institution_ids":["https://openalex.org/I130769515"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5034067036","display_name":"Naveen Muralimanohar","orcid":null},"institutions":[{"id":"https://openalex.org/I1324840837","display_name":"Hewlett-Packard (United States)","ror":"https://ror.org/059rn9488","country_code":"US","type":"company","lineage":["https://openalex.org/I1324840837"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Naveen Muralimanohar","raw_affiliation_strings":["HP Labs"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"HP Labs","institution_ids":["https://openalex.org/I1324840837"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5087056095","display_name":"Rajeev Balasubramonian","orcid":"https://orcid.org/0009-0009-4093-5904"},"institutions":[{"id":"https://openalex.org/I1324840837","display_name":"Hewlett-Packard (United States)","ror":"https://ror.org/059rn9488","country_code":"US","type":"company","lineage":["https://openalex.org/I1324840837"]},{"id":"https://openalex.org/I223532165","display_name":"University of Utah","ror":"https://ror.org/03r0ha626","country_code":"US","type":"education","lineage":["https://openalex.org/I223532165"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Rajeev Balasubramonian","raw_affiliation_strings":["HP Labs","University of Utah"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"HP Labs","institution_ids":["https://openalex.org/I1324840837"]},{"raw_affiliation_string":"University of Utah","institution_ids":["https://openalex.org/I223532165"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100375924","display_name":"Tao Zhang","orcid":"https://orcid.org/0000-0003-3782-0478"},"institutions":[{"id":"https://openalex.org/I130769515","display_name":"Pennsylvania State University","ror":"https://ror.org/04p491231","country_code":"US","type":"education","lineage":["https://openalex.org/I130769515"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Tao Zhang","raw_affiliation_strings":["Pennsylvania State University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Pennsylvania State University","institution_ids":["https://openalex.org/I130769515"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5054894631","display_name":"Shimeng Yu","orcid":"https://orcid.org/0000-0002-0068-3652"},"institutions":[{"id":"https://openalex.org/I55732556","display_name":"Arizona State University","ror":"https://ror.org/03efmqc40","country_code":"US","type":"education","lineage":["https://openalex.org/I55732556"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Shimeng Yu","raw_affiliation_strings":["Arizona State University"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Arizona State University","institution_ids":["https://openalex.org/I55732556"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100385336","display_name":"Yuan Xie","orcid":"https://orcid.org/0000-0003-2093-1788"},"institutions":[{"id":"https://openalex.org/I130769515","display_name":"Pennsylvania State University","ror":"https://ror.org/04p491231","country_code":"US","type":"education","lineage":["https://openalex.org/I130769515"]},{"id":"https://openalex.org/I154570441","display_name":"University of California, Santa Barbara","ror":"https://ror.org/02t274463","country_code":"US","type":"education","lineage":["https://openalex.org/I154570441"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yuan Xie","raw_affiliation_strings":["Pennsylvania State University","University of California, Santa Barbara"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Pennsylvania State University","institution_ids":["https://openalex.org/I130769515"]},{"raw_affiliation_string":"University of California, Santa Barbara","institution_ids":["https://openalex.org/I154570441"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":331,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"476","last_page":"488"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/resistive-random-access-memory","display_name":"Resistive random-access memory","score":0.8889268636703491},{"id":"https://openalex.org/keywords/crossbar-switch","display_name":"Crossbar switch","score":0.8759009838104248},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7522648572921753},{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.6276942491531372},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.5940446853637695},{"id":"https://openalex.org/keywords/cas-latency","display_name":"CAS latency","score":0.553336501121521},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.5316586494445801},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.44483253359794617},{"id":"https://openalex.org/keywords/memory-architecture","display_name":"Memory architecture","score":0.4337872862815857},{"id":"https://openalex.org/keywords/registered-memory","display_name":"Registered memory","score":0.42726603150367737},{"id":"https://openalex.org/keywords/microarchitecture","display_name":"Microarchitecture","score":0.4169505834579468},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.41510120034217834},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3709174394607544},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.36604073643684387},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.355959415435791},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.35146385431289673},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.32486867904663086},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.20429956912994385},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1243526041507721},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.11451798677444458},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.08860239386558533}],"concepts":[{"id":"https://openalex.org/C182019814","wikidata":"https://www.wikidata.org/wiki/Q1143830","display_name":"Resistive random-access memory","level":3,"score":0.8889268636703491},{"id":"https://openalex.org/C29984679","wikidata":"https://www.wikidata.org/wiki/Q1929149","display_name":"Crossbar switch","level":2,"score":0.8759009838104248},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7522648572921753},{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.6276942491531372},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.5940446853637695},{"id":"https://openalex.org/C189930140","wikidata":"https://www.wikidata.org/wiki/Q1112878","display_name":"CAS latency","level":4,"score":0.553336501121521},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.5316586494445801},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.44483253359794617},{"id":"https://openalex.org/C2779602883","wikidata":"https://www.wikidata.org/wiki/Q15544750","display_name":"Memory architecture","level":2,"score":0.4337872862815857},{"id":"https://openalex.org/C93446704","wikidata":"https://www.wikidata.org/wiki/Q449328","display_name":"Registered memory","level":3,"score":0.42726603150367737},{"id":"https://openalex.org/C107598950","wikidata":"https://www.wikidata.org/wiki/Q259864","display_name":"Microarchitecture","level":2,"score":0.4169505834579468},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.41510120034217834},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3709174394607544},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.36604073643684387},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.355959415435791},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.35146385431289673},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.32486867904663086},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.20429956912994385},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1243526041507721},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.11451798677444458},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.08860239386558533}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/hpca.2015.7056056","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hpca.2015.7056056","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)","raw_type":"proceedings-article"},{"id":"pmh:oai:repository.hkust.edu.hk:1783.1-133441","is_oa":false,"landing_page_url":"http://www.scopus.com/record/display.url?eid=2-s2.0-84934298890&origin=inward","pdf_url":null,"source":{"id":"https://openalex.org/S4306401796","display_name":"Rare & Special e-Zone (The Hong Kong University of Science and Technology)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I200769079","host_organization_name":"Hong Kong University of Science and Technology","host_organization_lineage":["https://openalex.org/I200769079"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Conference paper"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.7699999809265137}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":56,"referenced_works":["https://openalex.org/W1980284740","https://openalex.org/W1981321271","https://openalex.org/W1983826793","https://openalex.org/W2004823737","https://openalex.org/W2010585077","https://openalex.org/W2010795939","https://openalex.org/W2018394736","https://openalex.org/W2020003503","https://openalex.org/W2025535306","https://openalex.org/W2036899386","https://openalex.org/W2041420601","https://openalex.org/W2041588416","https://openalex.org/W2048588974","https://openalex.org/W2053376043","https://openalex.org/W2056222607","https://openalex.org/W2078260102","https://openalex.org/W2082070657","https://openalex.org/W2084007230","https://openalex.org/W2088207049","https://openalex.org/W2091988614","https://openalex.org/W2093899855","https://openalex.org/W2097823832","https://openalex.org/W2098463429","https://openalex.org/W2099874423","https://openalex.org/W2102255233","https://openalex.org/W2102449048","https://openalex.org/W2108048675","https://openalex.org/W2112753327","https://openalex.org/W2112768159","https://openalex.org/W2115500527","https://openalex.org/W2116826022","https://openalex.org/W2117788358","https://openalex.org/W2119092821","https://openalex.org/W2121795083","https://openalex.org/W2124165274","https://openalex.org/W2125514677","https://openalex.org/W2127419525","https://openalex.org/W2130154972","https://openalex.org/W2130657217","https://openalex.org/W2135393827","https://openalex.org/W2138661001","https://openalex.org/W2143027322","https://openalex.org/W2147657366","https://openalex.org/W2153701544","https://openalex.org/W2155462575","https://openalex.org/W2155551886","https://openalex.org/W2157808045","https://openalex.org/W2161678437","https://openalex.org/W2162752393","https://openalex.org/W2165310699","https://openalex.org/W2178102281","https://openalex.org/W3099470245","https://openalex.org/W3140396777","https://openalex.org/W4214773815","https://openalex.org/W6671183045","https://openalex.org/W6675347859"],"related_works":["https://openalex.org/W3008068282","https://openalex.org/W2065759842","https://openalex.org/W2557931434","https://openalex.org/W2185658074","https://openalex.org/W2023569851","https://openalex.org/W2090814603","https://openalex.org/W1805046480","https://openalex.org/W3089341786","https://openalex.org/W2132401245","https://openalex.org/W2155643858"],"abstract_inverted_index":{"The":[0,118,261],"scalability":[1],"of":[2,13,79,101,121,127,217,236,258,271],"DRAM":[3,43],"faces":[4],"challenges":[5],"from":[6,87],"increasing":[7],"power":[8],"consumption":[9],"and":[10,32,59,115,146,166,174,187,243,256,285,293],"the":[11,128,163,196,212,215,234,269],"difficulty":[12],"building":[14],"high":[15,54,60,84],"aspect":[16],"ratio":[17],"capacitors.":[18],"Consequently,":[19],"emerging":[20],"memory":[21,81,277],"technologies":[22],"including":[23],"Phase":[24],"Change":[25],"Memory":[26],"(PCM),":[27],"Spin-Transfer":[28],"Torque":[29],"RAM":[30,34],"(STT-RAM),":[31],"Resistive":[33],"(ReRAM)":[35],"are":[36,96],"being":[37],"actively":[38],"pursued":[39],"as":[40,53,183],"replacements":[41],"for":[42,151],"memory.":[44],"Among":[45],"these":[46],"candidates,":[47],"ReRAM":[48,102],"has":[49,294],"superior":[50],"characteristics":[51],"such":[52,182],"density,":[55],"low":[56],"write":[57,113,134,144,172,193,225],"energy,":[58],"endurance,":[61],"making":[62],"it":[63],"a":[64,76,122,125,133,199,218,245,259,272,282],"very":[65],"attractive":[66],"cost-efficient":[67],"alternative":[68],"to":[69,191,208,301],"DRAM.":[70],"In":[71],"this":[72],"paper,":[73],"we":[74,161,241],"present":[75],"comprehensive":[77],"study":[78,162],"ReRAM-based":[80,275],"systems.":[82],"ReRAM's":[83,139],"density":[85],"comes":[86],"its":[88,143,223],"unique":[89],"crossbar":[90,105,123,164],"architecture":[91,106,165,197,267],"where":[92],"some":[93],"peripheral":[94],"circuits":[95],"laid":[97],"below":[98],"multiple":[99],"layers":[100],"cells.":[103],"A":[104],"introduces":[107],"special":[108],"constraints":[109],"on":[110,222,239,254,291],"operating":[111],"voltages,":[112],"latency,":[114,173],"array":[116],"size.":[117],"access":[119],"latency":[120,148,226,255],"is":[124,206,227],"function":[126],"data":[129,175,203],"patterns":[130],"involved":[131],"in":[132],"operation.":[135],"These":[136],"combined":[137],"with":[138],"exponential":[140],"relationship":[141],"between":[142],"voltage":[145,170],"switching":[147],"provide":[149],"opportunities":[150],"architectural":[152],"optimizations.":[153],"This":[154],"paper":[155],"makes":[156,250],"several":[157],"key":[158],"contributions.":[159],"First,":[160],"describe":[167],"trade-offs":[168],"involving":[169],"drop,":[171],"pattern.":[176],"We":[177],"then":[178],"analyze":[179],"microarchitectural":[180],"enhancements":[181],"double-sided":[184],"ground":[185],"biasing":[186],"multiphase":[188],"reset":[189],"operations":[190],"improve":[192],"performance.":[194],"At":[195],"level,":[198],"simple":[200],"compression":[201],"based":[202,221,253],"encoding":[204],"scheme":[205],"proposed":[207],"further":[209],"bring":[210],"down":[211],"latency.":[213],"As":[214],"compressibility":[216],"block":[219],"varies":[220],"content,":[224],"not":[228],"uniform":[229],"across":[230],"blocks.":[231],"To":[232],"mitigate":[233],"impact":[235],"slow":[237],"writes":[238],"performance,":[240],"propose":[242],"evaluate":[244],"novel":[246],"scheduling":[247],"policy":[248],"that":[249,265],"writing":[251],"decisions":[252],"activity":[257],"bank.":[260],"experimental":[262],"results":[263],"show":[264],"our":[266],"improves":[268],"performance":[270,298],"system":[273],"using":[274],"main":[276],"by":[278],"about":[279],"44%":[280],"over":[281,287],"conservative":[283],"baseline":[284,290],"14%":[286],"an":[288,302],"aggressive":[289],"average,":[292],"less":[295],"than":[296],"10%":[297],"degradation":[299],"compared":[300],"ideal":[303],"DRAM-only":[304],"system.":[305]},"counts_by_year":[{"year":2026,"cited_by_count":5},{"year":2025,"cited_by_count":11},{"year":2024,"cited_by_count":8},{"year":2023,"cited_by_count":26},{"year":2022,"cited_by_count":22},{"year":2021,"cited_by_count":39},{"year":2020,"cited_by_count":38},{"year":2019,"cited_by_count":59},{"year":2018,"cited_by_count":54},{"year":2017,"cited_by_count":28},{"year":2016,"cited_by_count":33},{"year":2015,"cited_by_count":8}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
