{"id":"https://openalex.org/W2100011668","doi":"https://doi.org/10.1109/hpca.2012.6168947","title":"TAP: A TLP-aware cache management policy for a CPU-GPU heterogeneous architecture","display_name":"TAP: A TLP-aware cache management policy for a CPU-GPU heterogeneous architecture","publication_year":2012,"publication_date":"2012-02-01","ids":{"openalex":"https://openalex.org/W2100011668","doi":"https://doi.org/10.1109/hpca.2012.6168947","mag":"2100011668"},"language":"en","primary_location":{"id":"doi:10.1109/hpca.2012.6168947","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hpca.2012.6168947","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE International Symposium on High-Performance Comp Architecture","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5016864052","display_name":"Jaekyu Lee","orcid":"https://orcid.org/0000-0002-0574-5381"},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Jaekyu Lee","raw_affiliation_strings":["School of Computer Science, Georgia Institute of Technology"],"affiliations":[{"raw_affiliation_string":"School of Computer Science, Georgia Institute of Technology","institution_ids":["https://openalex.org/I130701444"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5000822269","display_name":"Hyesoon Kim","orcid":"https://orcid.org/0000-0002-6061-7825"},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Hyesoon Kim","raw_affiliation_strings":["School of Computer Science, Georgia Institute of Technology"],"affiliations":[{"raw_affiliation_string":"School of Computer Science, Georgia Institute of Technology","institution_ids":["https://openalex.org/I130701444"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5016864052"],"corresponding_institution_ids":["https://openalex.org/I130701444"],"apc_list":null,"apc_paid":null,"fwci":18.8538,"has_fulltext":false,"cited_by_count":133,"citation_normalized_percentile":{"value":0.99634626,"is_in_top_1_percent":true,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":100},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"12"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10101","display_name":"Cloud Computing and Resource Management","score":0.9965000152587891,"subfield":{"id":"https://openalex.org/subfields/1710","display_name":"Information Systems"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8689756393432617},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.7839374542236328},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6120540499687195},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.6060584187507629},{"id":"https://openalex.org/keywords/cache-coloring","display_name":"Cache coloring","score":0.6016790270805359},{"id":"https://openalex.org/keywords/cache-pollution","display_name":"Cache pollution","score":0.5867727994918823},{"id":"https://openalex.org/keywords/general-purpose-computing-on-graphics-processing-units","display_name":"General-purpose computing on graphics processing units","score":0.566078245639801},{"id":"https://openalex.org/keywords/smart-cache","display_name":"Smart Cache","score":0.5623720288276672},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.4321277439594269},{"id":"https://openalex.org/keywords/page-cache","display_name":"Page cache","score":0.43211862444877625},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.4278028607368469},{"id":"https://openalex.org/keywords/central-processing-unit","display_name":"Central processing unit","score":0.41703659296035767},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.34732499718666077},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3217077851295471},{"id":"https://openalex.org/keywords/graphics","display_name":"Graphics","score":0.07354855537414551}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8689756393432617},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.7839374542236328},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6120540499687195},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.6060584187507629},{"id":"https://openalex.org/C201148951","wikidata":"https://www.wikidata.org/wiki/Q5015976","display_name":"Cache coloring","level":4,"score":0.6016790270805359},{"id":"https://openalex.org/C113166858","wikidata":"https://www.wikidata.org/wiki/Q5015981","display_name":"Cache pollution","level":5,"score":0.5867727994918823},{"id":"https://openalex.org/C50630238","wikidata":"https://www.wikidata.org/wiki/Q971505","display_name":"General-purpose computing on graphics processing units","level":3,"score":0.566078245639801},{"id":"https://openalex.org/C167713795","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"Smart Cache","level":5,"score":0.5623720288276672},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.4321277439594269},{"id":"https://openalex.org/C36340418","wikidata":"https://www.wikidata.org/wiki/Q7124288","display_name":"Page cache","level":5,"score":0.43211862444877625},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.4278028607368469},{"id":"https://openalex.org/C49154492","wikidata":"https://www.wikidata.org/wiki/Q5300","display_name":"Central processing unit","level":2,"score":0.41703659296035767},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.34732499718666077},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3217077851295471},{"id":"https://openalex.org/C21442007","wikidata":"https://www.wikidata.org/wiki/Q1027879","display_name":"Graphics","level":2,"score":0.07354855537414551}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/hpca.2012.6168947","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hpca.2012.6168947","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE International Symposium on High-Performance Comp Architecture","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"},{"id":"https://openalex.org/F4320306084","display_name":"U.S. Department of Energy","ror":"https://ror.org/01bj3aw27"},{"id":"https://openalex.org/F4320309480","display_name":"Nvidia","ror":"https://ror.org/03jdj4y14"},{"id":"https://openalex.org/F4320338291","display_name":"Sandia National Laboratories","ror":"https://ror.org/01apwpt12"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":27,"referenced_works":["https://openalex.org/W1554154077","https://openalex.org/W1619746206","https://openalex.org/W1967474856","https://openalex.org/W1968029317","https://openalex.org/W1992180455","https://openalex.org/W2005395913","https://openalex.org/W2029577083","https://openalex.org/W2080592089","https://openalex.org/W2096572124","https://openalex.org/W2109426995","https://openalex.org/W2110638983","https://openalex.org/W2111804126","https://openalex.org/W2120692212","https://openalex.org/W2123990034","https://openalex.org/W2124350608","https://openalex.org/W2128046183","https://openalex.org/W2129816520","https://openalex.org/W2135089498","https://openalex.org/W2143773524","https://openalex.org/W2150196852","https://openalex.org/W2160996172","https://openalex.org/W3144376511","https://openalex.org/W4214898277","https://openalex.org/W4240197237","https://openalex.org/W4244814458","https://openalex.org/W4251173935","https://openalex.org/W6657687284"],"related_works":["https://openalex.org/W2133489088","https://openalex.org/W2118932116","https://openalex.org/W2114386333","https://openalex.org/W2535115842","https://openalex.org/W2126408955","https://openalex.org/W2396934146","https://openalex.org/W2363769136","https://openalex.org/W2148571123","https://openalex.org/W2734782074","https://openalex.org/W2539712666"],"abstract_inverted_index":{"Combining":[0],"CPUs":[1,71],"and":[2,51,72,84,109,151,162,171,179,187],"GPUs":[3,73],"on":[4,21,63,175],"the":[5,28,68,79,135],"same":[6],"chip":[7],"has":[8,60],"become":[9],"a":[10,116,127,138],"popular":[11],"architectural":[12],"trend.":[13],"However,":[14],"these":[15],"heterogeneous":[16,65,123,177],"architectures":[17],"put":[18],"more":[19],"pressure":[20],"shared":[22,43],"resource":[23],"management.":[24],"In":[25,111],"particular,":[26],"managing":[27],"last-level":[29],"cache":[30,44,49,53,57,118,144],"(LLC)":[31],"is":[32],"very":[33],"critical":[34],"to":[35,78,130],"performance.":[36],"Lately,":[37],"many":[38,98],"researchers":[39],"have":[40],"proposed":[41],"several":[42],"management":[45,58,119,145],"mechanisms,":[46],"including":[47],"dynamic":[48],"partitioning":[50],"promotion-based":[52],"management,":[54],"but":[55],"no":[56],"work":[59],"been":[61],"done":[62],"CPU-GPU":[64,122],"architectures.":[66,124],"Sharing":[67],"LLC":[69],"between":[70],"brings":[74],"new":[75,159],"challenges":[76],"due":[77],"different":[80],"characteristics":[81],"of":[82,137],"CPU":[83,90],"GPGPU":[85,99,139],"applications.":[86],"Unlike":[87],"most":[88],"memory-intensive":[89],"benchmarks":[91],"that":[92],"hide":[93,101],"memory":[94,102],"latency":[95,103],"with":[96],"caching,":[97],"applications":[100],"by":[104,142,167,183],"combining":[105],"thread-level":[106],"parallelism":[107],"(TLP)":[108],"caching.":[110],"this":[112],"paper,":[113],"we":[114,156],"propose":[115,157],"TLP-aware":[117],"policy":[120],"for":[121],"We":[125],"introduce":[126],"core-sampling":[128],"mechanism":[129],"detect":[131],"how":[132],"caching":[133],"affects":[134],"performance":[136,166,182],"application.":[140],"Inspired":[141],"previous":[143],"schemes,":[146],"Utility-based":[147],"Cache":[148],"Partitioning":[149],"(UCP)":[150],"Re-Reference":[152],"Interval":[153],"Prediction":[154],"(RRIP),":[155],"two":[158],"mechanisms:":[160],"TAP-UCP":[161,164],"TAP-RRIP.":[163],"improves":[165,181],"5%":[168],"over":[169,173,185,189],"UCP":[170],"11%":[172],"LRU":[174],"152":[176],"workloads,":[178],"TAP-RRIP":[180],"9%":[184],"RRIP":[186],"12%":[188],"LRU.":[190]},"counts_by_year":[{"year":2025,"cited_by_count":3},{"year":2024,"cited_by_count":3},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":4},{"year":2021,"cited_by_count":4},{"year":2020,"cited_by_count":3},{"year":2019,"cited_by_count":8},{"year":2018,"cited_by_count":18},{"year":2017,"cited_by_count":14},{"year":2016,"cited_by_count":10},{"year":2015,"cited_by_count":23},{"year":2014,"cited_by_count":23},{"year":2013,"cited_by_count":16},{"year":2012,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
