{"id":"https://openalex.org/W2153173314","doi":"https://doi.org/10.1109/hpca.2003.1183522","title":"Front-end policies for improved issue efficiency in SMT processors","display_name":"Front-end policies for improved issue efficiency in SMT processors","publication_year":2003,"publication_date":"2003-08-27","ids":{"openalex":"https://openalex.org/W2153173314","doi":"https://doi.org/10.1109/hpca.2003.1183522","mag":"2153173314"},"language":"en","primary_location":{"id":"doi:10.1109/hpca.2003.1183522","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hpca.2003.1183522","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"The Ninth International Symposium on High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings.","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":null,"display_name":"A. El-Moursy","orcid":null},"institutions":[{"id":"https://openalex.org/I5388228","display_name":"University of Rochester","ror":"https://ror.org/022kthw22","country_code":"US","type":"education","lineage":["https://openalex.org/I5388228"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"A. El-Moursy","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Rochester, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Rochester, USA","institution_ids":["https://openalex.org/I5388228"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5009386140","display_name":"David H. Albonesi","orcid":null},"institutions":[{"id":"https://openalex.org/I5388228","display_name":"University of Rochester","ror":"https://ror.org/022kthw22","country_code":"US","type":"education","lineage":["https://openalex.org/I5388228"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"D.H. Albonesi","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Rochester, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Rochester, USA","institution_ids":["https://openalex.org/I5388228"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I5388228"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":107,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"31","last_page":"40"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10715","display_name":"Distributed and Parallel Computing Systems","score":0.9962999820709229,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9923999905586243,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8345457315444946},{"id":"https://openalex.org/keywords/queue","display_name":"Queue","score":0.7649422287940979},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.523522138595581},{"id":"https://openalex.org/keywords/threading","display_name":"Threading (protein sequence)","score":0.4522349238395691},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.1086040735244751}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8345457315444946},{"id":"https://openalex.org/C160403385","wikidata":"https://www.wikidata.org/wiki/Q220543","display_name":"Queue","level":2,"score":0.7649422287940979},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.523522138595581},{"id":"https://openalex.org/C200307862","wikidata":"https://www.wikidata.org/wiki/Q7797175","display_name":"Threading (protein sequence)","level":3,"score":0.4522349238395691},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.1086040735244751},{"id":"https://openalex.org/C46141821","wikidata":"https://www.wikidata.org/wiki/Q209402","display_name":"Nuclear magnetic resonance","level":1,"score":0.0},{"id":"https://openalex.org/C47701112","wikidata":"https://www.wikidata.org/wiki/Q735188","display_name":"Protein structure","level":2,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":4,"locations":[{"id":"doi:10.1109/hpca.2003.1183522","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hpca.2003.1183522","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"The Ninth International Symposium on High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings.","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.11.5041","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.11.5041","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.ece.rochester.edu/~albonesi/research/papers/hpca03_1.ps","raw_type":"text"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.12.8479","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.12.8479","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.cs.arizona.edu/hpca9/HPCA-PDFs/04-elmoursy.pdf","raw_type":"text"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.126.1740","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.126.1740","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.ece.rochester.edu/~albonesi/research/papers/hpca03_1.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":37,"referenced_works":["https://openalex.org/W150323568","https://openalex.org/W1552561789","https://openalex.org/W1571008568","https://openalex.org/W1584321010","https://openalex.org/W1785834895","https://openalex.org/W2039631685","https://openalex.org/W2106625514","https://openalex.org/W2107241550","https://openalex.org/W2112505501","https://openalex.org/W2112833506","https://openalex.org/W2118532220","https://openalex.org/W2119874774","https://openalex.org/W2120230074","https://openalex.org/W2122438621","https://openalex.org/W2129548165","https://openalex.org/W2131556574","https://openalex.org/W2138351227","https://openalex.org/W2153512189","https://openalex.org/W2155470191","https://openalex.org/W2156174665","https://openalex.org/W2161864047","https://openalex.org/W2171706011","https://openalex.org/W3142147837","https://openalex.org/W4231178640","https://openalex.org/W4236318606","https://openalex.org/W4236892585","https://openalex.org/W4253011005","https://openalex.org/W4285719527","https://openalex.org/W6606148001","https://openalex.org/W6634224414","https://openalex.org/W6634836887","https://openalex.org/W6638104371","https://openalex.org/W6675685008","https://openalex.org/W6678441313","https://openalex.org/W6679308475","https://openalex.org/W6679474879","https://openalex.org/W6792903772"],"related_works":["https://openalex.org/W4391375266","https://openalex.org/W2899084033","https://openalex.org/W2748952813","https://openalex.org/W1554180614","https://openalex.org/W4232948691","https://openalex.org/W2069834727","https://openalex.org/W4300126630","https://openalex.org/W2167671877","https://openalex.org/W2380523273","https://openalex.org/W2020139636"],"abstract_inverted_index":{"The":[0],"performance":[1],"and":[2,17,31,84],"power":[3],"optimization":[4],"of":[5,65,108,116],"dynamic":[6],"superscalar":[7],"microprocessors":[8],"requires":[9],"striking":[10],"a":[11,46,105],"careful":[12,39],"balance":[13],"between":[14],"exploiting":[15],"parallelism":[16],"hardware":[18],"simplification.":[19],"Hardware":[20],"structures":[21],"which":[22],"are":[23],"needlessly":[24],"complex":[25],"may":[26],"exacerbate":[27],"critical":[28],"timing":[29],"paths":[30],"dissipate":[32],"extra":[33],"power.":[34],"One":[35],"such":[36],"structure":[37],"requiring":[38],"design":[40],"is":[41,52],"the":[42,62,66,81,113,118,123],"issue":[43,57,87,109,124,136],"queue.":[44],"In":[45,71],"simultaneous":[47],"multi-threading":[48],"(SMT)":[49],"processor":[50,132],"it":[51],"particularly":[53],"challenging":[54],"to":[55,61],"achieve":[56],"queue":[58,67,88,110,125,137],"simplification":[59],"due":[60],"increased":[63],"utilization":[64],"afforded":[68],"by":[69,127],"multi-threading.":[70],"this":[72],"paper":[73],"we":[74],"propose":[75],"new":[76],"front-end":[77],"policies":[78,97,121],"that":[79],"reduce":[80,122],"required":[82],"integer":[83],"floating":[85],"point":[86],"sizes":[89],"in":[90],"SMT":[91,131],"processors.":[92],"We":[93],"explore":[94],"both":[95],"general":[96],"as":[98,100],"well":[99],"those":[101],"directed":[102],"towards":[103],"alleviating":[104],"particular":[106],"cause":[107],"inefficiency.":[111],"For":[112],"same":[114],"level":[115],"performance,":[117],"most":[119],"effective":[120],"occupancy":[126],"33%":[128],"for":[129],"an":[130],"with":[133],"appropriately":[134],"sized":[135],"resources.":[138]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2021,"cited_by_count":3},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":3},{"year":2012,"cited_by_count":5}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}