{"id":"https://openalex.org/W2621371400","doi":"https://doi.org/10.1109/hotchips.2016.7936224","title":"A new \u00d786 core architecture for the next generation of computing","display_name":"A new \u00d786 core architecture for the next generation of computing","publication_year":2016,"publication_date":"2016-08-01","ids":{"openalex":"https://openalex.org/W2621371400","doi":"https://doi.org/10.1109/hotchips.2016.7936224","mag":"2621371400"},"language":"en","primary_location":{"id":"doi:10.1109/hotchips.2016.7936224","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hotchips.2016.7936224","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE Hot Chips 28 Symposium (HCS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5019517505","display_name":"Mike Clark","orcid":null},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Mike Clark","raw_affiliation_strings":["AMD, United States of America"],"affiliations":[{"raw_affiliation_string":"AMD, United States of America","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5019517505"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":5.9914,"has_fulltext":false,"cited_by_count":29,"citation_normalized_percentile":{"value":0.96877939,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"19"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.8549000024795532,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.8549000024795532,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10715","display_name":"Distributed and Parallel Computing Systems","score":0.8342999815940857,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8125190734863281},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.6659369468688965},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.6199816465377808},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.504327654838562},{"id":"https://openalex.org/keywords/core","display_name":"Core (optical fiber)","score":0.5036064982414246},{"id":"https://openalex.org/keywords/many-core","display_name":"Many core","score":0.4385491907596588},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.41964611411094666},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.37293198704719543},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3337353765964508},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.10201287269592285}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8125190734863281},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.6659369468688965},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6199816465377808},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.504327654838562},{"id":"https://openalex.org/C2164484","wikidata":"https://www.wikidata.org/wiki/Q5170150","display_name":"Core (optical fiber)","level":2,"score":0.5036064982414246},{"id":"https://openalex.org/C3020431745","wikidata":"https://www.wikidata.org/wiki/Q25325220","display_name":"Many core","level":2,"score":0.4385491907596588},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.41964611411094666},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.37293198704719543},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3337353765964508},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.10201287269592285},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/hotchips.2016.7936224","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hotchips.2016.7936224","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE Hot Chips 28 Symposium (HCS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2394430006","https://openalex.org/W1516700698","https://openalex.org/W2384472584","https://openalex.org/W163366574","https://openalex.org/W2105755249","https://openalex.org/W135500268","https://openalex.org/W2803402499","https://openalex.org/W2099708455","https://openalex.org/W2371762158","https://openalex.org/W4391230627"],"abstract_inverted_index":{"Presents":[0],"a":[1],"collection":[2],"of":[3],"slides":[4],"covering":[5],"the":[6],"following":[7],"topics:":[8],"high":[9],"level":[10],"architecture;":[11],"floating":[12],"point;":[13],"cache":[14],"system;":[15],"and":[16],"ISA":[17],"extensions.":[18]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":2},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":4},{"year":2019,"cited_by_count":7},{"year":2018,"cited_by_count":7},{"year":2017,"cited_by_count":5}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
