{"id":"https://openalex.org/W2463414072","doi":"https://doi.org/10.1109/hotchips.2012.7476501","title":"The Intel\u00ae Xeon\u00ae processor E5 family architecture, power efficiency, and performance","display_name":"The Intel\u00ae Xeon\u00ae processor E5 family architecture, power efficiency, and performance","publication_year":2012,"publication_date":"2012-08-01","ids":{"openalex":"https://openalex.org/W2463414072","doi":"https://doi.org/10.1109/hotchips.2012.7476501","mag":"2463414072"},"language":"en","primary_location":{"id":"doi:10.1109/hotchips.2012.7476501","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hotchips.2012.7476501","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE Hot Chips 24 Symposium (HCS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5109284484","display_name":"Jeff Gilbert","orcid":null},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Jeff Gilbert","raw_affiliation_strings":["Icergi Ltd., Dublin, Ireland"],"affiliations":[{"raw_affiliation_string":"Icergi Ltd., Dublin, Ireland","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5108379405","display_name":"Mark Rowland","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Mark Rowland","raw_affiliation_strings":["Icergi Ltd., Dublin, Ireland"],"affiliations":[{"raw_affiliation_string":"Icergi Ltd., Dublin, Ireland","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5109284484"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.26794079,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"25"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.8848000168800354,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.8848000168800354,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7376126050949097},{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.696757435798645},{"id":"https://openalex.org/keywords/xeon","display_name":"Xeon","score":0.6766109466552734},{"id":"https://openalex.org/keywords/cas-latency","display_name":"CAS latency","score":0.5896738767623901},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5753042101860046},{"id":"https://openalex.org/keywords/xeon-phi","display_name":"Xeon Phi","score":0.5642445683479309},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.5451518893241882},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.519416093826294},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.49665361642837524},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.4216790199279785},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.412350594997406},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4020630717277527},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.29663753509521484},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.2673284113407135},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.133765310049057},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.062111496925354004}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7376126050949097},{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.696757435798645},{"id":"https://openalex.org/C145108525","wikidata":"https://www.wikidata.org/wiki/Q656154","display_name":"Xeon","level":2,"score":0.6766109466552734},{"id":"https://openalex.org/C189930140","wikidata":"https://www.wikidata.org/wiki/Q1112878","display_name":"CAS latency","level":4,"score":0.5896738767623901},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5753042101860046},{"id":"https://openalex.org/C96972482","wikidata":"https://www.wikidata.org/wiki/Q1049168","display_name":"Xeon Phi","level":2,"score":0.5642445683479309},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.5451518893241882},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.519416093826294},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.49665361642837524},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.4216790199279785},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.412350594997406},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4020630717277527},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.29663753509521484},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.2673284113407135},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.133765310049057},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.062111496925354004},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/hotchips.2012.7476501","is_oa":false,"landing_page_url":"https://doi.org/10.1109/hotchips.2012.7476501","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE Hot Chips 24 Symposium (HCS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8999999761581421,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W1974923383","https://openalex.org/W2475524688","https://openalex.org/W2739740241","https://openalex.org/W2085105049","https://openalex.org/W4293430534","https://openalex.org/W2342813629","https://openalex.org/W2592417500","https://openalex.org/W3150934690","https://openalex.org/W4297812927","https://openalex.org/W2022666014"],"abstract_inverted_index":{"Presents":[0],"a":[1],"collection":[2],"of":[3],"slides":[4],"covering":[5],"the":[6],"following":[7],"topics:":[8],"Sandy":[9],"Bridge":[10],"core;":[11],"SNB-EP":[12],"performance;":[13],"Thurley":[14],"platform;":[15],"CPU;":[16],"DRAM;":[17],"and":[18],"memory":[19],"latency":[20],"optimization.":[21]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2018,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}